Semiconductor device containing MIM capacitor and fabrication method

1. A method of fabricating a semiconductor device containing an MIM capacitor, comprising:

providing a first interlayer dielectric layer to cover a substrate;

providing a metal interconnect layer in the substrate;

forming a metal-insulator-metal (MIM) capacitor on the first interlayer dielectric layer, wherein the MIM capacitor includes a bottom electrode layer and a top electrode layer that are isolated from and laterally staggered with one another;

forming a second interlayer dielectric layer to cover both the MIM capacitor and the first interlayer dielectric layer; and

forming a first conductive plug and a second conductive plug each passing through the second interlayer dielectric layer, wherein the first conductive plug contacts a sidewall and a surface portion of the top electrode layer of the MIM capacitor and the second conductive plug contacts a sidewall and a surface portion of the bottom electrode layer of the MIM capacitor, and wherein at least one of the first conductive plug and the second conductive plug passes through the first interlayer dielectric layer and connects electrically with the metal interconnect layer.

2. The fabrication method of claim 1 , wherein forming the MIM capacitor includes:

forming the bottom electrode layer on the first interlayer dielectric layer,

forming an isolation thin film covering the bottom electrode layer,

forming a top electrode thin film covering the isolation thin film,

forming a first mask layer on the top electrode thin film,

etching the top electrode thin film and the isolation thin film using the first mask layer as an etch mask to expose the bottom electrode layer to form an isolation layer and a top electrode layer covering the isolation layer, and

removing the first mask layer upon formation of the isolation layer and the top electrode layer.

3. The fabrication method of claim 1 , wherein forming the first conductive plug and the second conductive plug includes:

forming a second mask layer on the second interlayer dielectric layer to define positions of the first conductive plug and the second conductive plug to be formed,

etching the second interlayer dielectric layer using the second mask layer as an etch mask to form a first opening to expose the sidewall and the surface portion of the top electrode layer of the MIM capacitor, and to form a second opening to expose the sidewall and the surface portion of the bottom electrode layer of the MIM capacitor, and

filling the first opening and the second opening with an electrically conductive material to form the first conductive plug and the second conductive plug, respectively.

4. The fabrication method of claim 1 , wherein the MIM capacitor is disposed in a region between neighboring metal interconnect layers in the substrate.

5. The fabrication method of claim 1 , further including forming an etching stop layer covering the substrate and the metal interconnect layer, wherein the first interlayer dielectric layer covers the etching stop layer.

6. The fabrication method of claim 1 , further including forming a metal hard-mask layer covering the second interlayer dielectric layer prior to forming the first conductive plug and the second conductive plug.

7. The fabrication method of claim 6 , wherein the metal hard-mask layer is made of titanium nitride.

8. The fabrication method of claim 1 , wherein the first interlayer dielectric layer is made of a low-K material, an ultra-low-K material, or an oxide, and the second interlayer dielectric layer is made of a low-K material, an ultra-low-K material, a fluorosilicate glass or an oxide.

9. The fabrication method of claim 1 , wherein the bottom electrode layer is made of titanium nitride, titanium, tantalum nitride, tantalum, or a combination thereof, and the top electrode layer is made of titanium nitride, titanium, tantalum nitride, tantalum, or a combination thereof.

10. The fabrication method of claim 1 , wherein only a portion of the bottom electrode layer faces or overlaps with only a portion of the top electrode layer, wherein the portion of the bottom electrode layer and the portion of the top electrode layer are isolated by an isolation layer.

11. A semiconductor device containing an MIM capacitor comprising:

a substrate;

a first interlayer dielectric layer covering the substrate;

a metal interconnect layer disposed in the substrate;

an MIM capacitor disposed on the first interlayer dielectric layer, wherein the MIM capacitor includes a bottom electrode layer and a top electrode layer that are isolated from and laterally staggered with one another;

a second interlayer dielectric layer covering both the MIM capacitor and the first interlayer dielectric layer; and

a first conductive plug and a second conductive plug passing through the second interlayer dielectric layer, wherein the first conductive plug contacts a sidewall and a surface portion of the top electrode layer of the MIM capacitor and the second conductive plug contacts a sidewall and a surface portion of the bottom electrode layer of the MIM capacitor, wherein at least one of the first conductive plug and the second conductive plug passes through the first interlayer dielectric layer and connects electrically to the metal interconnect layer.

12. The semiconductor device of claim 11 , wherein the MIM capacitor is disposed in a region between neighboring metal interconnect layers.

13. The semiconductor device of claim 11 , further including an etching stop layer covering the substrate and the metal interconnect layer, wherein the first interlayer dielectric layer covers the etching stop layer.

14. The semiconductor device of claim 11 , wherein only a portion of the bottom electrode layer faces or overlaps with only a portion of the top electrode layer, wherein the portion of the bottom electrode layer and the portion of the top electrode layer are isolated by an isolation layer.

15. The semiconductor device of claim 11 , wherein the first interlayer dielectric layer is made of a low-K material, an ultra-low-K material, or an oxide, and the second interlayer dielectric layer is made of a low-K material, an ultra-low-K material, a fluorosilicate glass or an oxide.

16. The semiconductor device of claim 11 , wherein each of the bottom electrode layer and the top electrode layer is made of a material including titanium nitride, titanium, tantalum nitride, tantalum, or a combination thereof.