Power management in semiconductor memory system
A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.
1. A computing apparatus, the apparatus comprising:
a memory interface device coupled to a memory module, and configured to receive a chip select, command, and address information, using a command-and-address-latency (CAL) mode transferred from a host memory controller, the host memory controller being coupled to the memory interface device, the memory module comprising a plurality of memory devices;
a control logic configured to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.
2. The apparatus of claim 1 wherein the memory interface device is a registering clock driver or a memory buffer.
3. The apparatus of claim 1 wherein each of the plurality of memory devices is a DDR4 SDRAM device or a memory device that includes a CAL mode that follows the definition of CAL mode as specified in JESD79-4.
4. The apparatus of claim 1 wherein the host computer is provided on a separate module; and wherein the memory interface device comprises a JEDEC standard DDR3 memory module interface or a DDR4 module interface.
5. The apparatus of claim 1 wherein the CAL mode is the command-and-address (CAL) mode as defined in JEDEC DDR4 SDRAM component specification, JESD79-4.
6. The apparatus of claim 1 wherein the control logic comprises a state machine that is operationally coupled to the input receiver for the chip-select signal and a set of control word registers, wherein, depending on the state of the chip-select signal and the setting in the control word registers, the state machine moves the command and address input receivers from a first power state to a second power state; and
wherein the first power state the input termination circuit are set to a first termination value, and in the second power state the input termination circuit is set to a second termination value.
7. The apparatus of claim 1 wherein the input termination circuit comprises a set of resistive elements arranged in parallel, wherein the number of parallel resistive elements connected in the input termination circuit determines the termination value provided by the input termination circuit.
8. A computing apparatus, the apparatus comprising:
a memory interface device configured for receiving a chip select signal at the memory interface device; the memory interface device configured for receiving an address signal at the memory interface device;
the memory interface device configure for receiving a command signal at the memory interface device;
the memory interface device configured for receiving a parity signal at the memory interface device;
the memory interface device configured for transferring the chip select signal having a first latency from the memory interface device to a rank of DRAM devices;
the memory interface device configured for transferring the address signal and the command signal having a second latency from the memory interface device to the rank of DRAM devices;
the memory interface device configured for transferring the parity signal having a third latency from the memory interface device to the rank of DRAM devices; and
a control configured to cause each of the DRAM devices to initiate a power state transition from a first power state to a second power state.
9. The apparatus of claim 8 wherein the control configured to cause is initiated by receiving the chip select signal at the rank of DRAM devices, the power state transition occurring at each of the input receiver devices associated with each of the DRAM devices.
10. The apparatus of claim 8 wherein the rank of DRAM devices is a plurality of ranks on a DIMM module.
11. The apparatus of claim 8 wherein the first latency is provided by the parameter t PDM , the pin-to-pin propagation delay time of a memory interface device including a DDR4 registering clock driver.
12. The apparatus of claim 8 wherein the second latency is provided by t CAL , the frequency-dependent command-and-address-latency value as defined by JESD79-4, the DDR4 SDRAM component specification.
13. The apparatus of claim 8 wherein the third latency is provided by t CAL −1.
14. The apparatus of claim 8 wherein the control is configured to initiate a no-operation (NOP) command when an input address parity error has been detected.