Methods of forming and programming memory devices with isolation structures
View Patent ↗Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.
1. A method of programming a memory device, comprising:
biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type;
biasing the second conductive region to a second voltage to forward bias a junction from the second conductive region to the first conductive region; and
injecting electrons into a charge-storage node of the selected memory cell from the second conductive region;
wherein the first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.
2. The method of claim 1 , further comprising:
floating the first conductive region while biasing the second conductive region to the second voltage.
3. The method of claim 1 , further comprising:
biasing the control gate of the selected memory cell to a positive voltage while biasing the second conductive region to a negative voltage.
4. The method of claim 1 , further comprising:
reverse biasing one or more source/drain regions contained in the first conductive region to collect the electrons accumulating at a surface of the first conductive region.
5. The method of claim 1 , further comprising:
biasing control gates of corresponding unselected memory cells of the memory device and contained within the dielectric isolation structure to flat-band or accumulation.
6. The method of claim 1 , further comprising:
biasing the control gate of the selected memory cell to a positive voltage;
floating the first conductive region having a p-type conductivity; and
biasing the second conductive region having an n++-type conductivity to a negative voltage.
7. The method of claim 1 , wherein injecting the electrons into the charge-storage node of the selected memory cell from the second conductive region comprises injecting the electrons over a gate dielectric barrier and into the charge-storage node of the selected memory cell.
8. The method of claim 1 , wherein injecting the electrons into the charge-storage node of the selected memory cell from the second conductive region comprises the electrons acquiring an energy greater than that of a gate dielectric barrier at a surface of the gate dielectric.
9. The method of claim 1 , further comprising reverse biasing a data line contact coupled to a source/drain region of a select gate coupled to the selected memory cell to collect the electrons accumulating at a surface of the first conductive region, wherein the source/drain region of the select gate is contained in the first conductive region.
10. The method of claim 1 , further comprising reverse biasing a source contact coupled to a source/drain region of a select gate coupled to the selected memory cell to collect the electrons accumulating at a surface of the first conductive region, wherein the source/drain region of the select gate is contained in the first conductive region.
11. A method of programming a memory device, comprising:
biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type;
biasing the second conductive region to a second voltage to forward bias a junction from the second conductive region to the first conductive region;
biasing the first conductive region to a third voltage between the first voltage and the second voltage; and
injecting electrons into a charge-storage node of the selected memory cell from the second conductive region;
wherein the first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.
12. The method of claim 11 , further comprising:
biasing the control gate of the selected memory cell to a positive voltage;
biasing the second conductive region having an n++-type conductivity to a negative voltage; and
biasing the first conductive region having a p-type conductivity to the third voltage between the positive voltage and the negative voltage.
13. The method of claim 12 , further comprising:
biasing the first conductive region to a ground potential.
14. The method of claim 11 , further comprising:
biasing the control gate of the selected memory cell to a positive voltage while biasing the second conductive region to a negative voltage; and
reverse biasing one or more source/drain regions contained in the first conductive region to collect electrons accumulating at a surface of the first conductive region.
15. The method of claim 11 , further comprising:
biasing control gates of corresponding unselected memory cells of the memory device and contained within the dielectric isolation structure to flat-band or accumulation.
16. The method of claim 11 , wherein injecting the electrons into the charge-storage node of the selected memory cell from the second conductive region comprises injecting the electrons over a gate dielectric barrier and into the charge-storage node of the selected memory cell.
17. A method of programming a memory device, comprising:
biasing a control gate of a selected memory cell of a string of memory cells of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type;
biasing the second conductive region to a second voltage to forward bias a junction from the second conductive region to the first conductive region;
injecting electrons into a charge-storage node of the selected memory cell from the second conductive region;
reverse biasing a source contact coupled to a source/drain region of a first select gate coupled to an end of the string of memory cells; and
reverse biasing a data line contact coupled to a source/drain region of a second select gate coupled to an opposite end of the string of memory cells;
wherein the first conductive region and the second conductive region are contained within a dielectric isolation structure in which the string of memory cells is contained.
18. The method of claim 17 , further comprising biasing the control gate of the selected memory cell to a positive voltage while biasing the second conductive region to a negative voltage.
19. The method of claim 17 , further comprising floating the first conductive region while biasing the second conductive region to the second voltage.
20. The method of claim 17 , further comprising biasing the first conductive region to a third voltage between the first voltage and the second voltage.