TRANSISTOR WITH REDUCTED PARASITIC
Parasitic thyristor action may be mitigated in semiconductor devices by placement of minority carrier traps, illustratively in the base(s) of bipolar transistors or the well of a CMOS transistor pair. The minority carrier traps include adjacent n and p regions which may be connected by a conductor.
1 . A transistor, comprising a minority carrier trap.
2 . The transistor of claim 1 in which said minority carrier trap is comprised of an n-doped region and a p doped region adjacent said n-doped region.
3 . The transistor of claim 2 in which said n and p doped region are connected by a conductor.
4 . The transistor of claim 3 having emitter, collector and base, comprising a minority carrier trap located within said base.
5 . The transistor of claim 3 in which said conductor is floating.
6 . The transistor of claim 4 in which said conductor is connected to the same voltage as the base.
7 . The transistor of claim 4 in which said minority carrier trap surrounds the emitter on at least three sides.
8 . The transistor of claim 4 in which said minority carrier trap surrounds the collector on at least three sides.
9 . The transistor of claim 1 in which said minority carrier trap comprises a plurality of n-doped regions and a plurality of p-doped regions arranged in a checkerboard pattern.
10 . The transistor of claim 1 in which said minority carrier trap comprises interdigitated fingers.
11 . The transistor of claim 3 in which said transistor is a MOS transistor and said minority carrier trap is in a doped well.
12 . The transistor of claim 1 in which said minority carrier trap includes one or more p doped and respective adjacent n doped regions.
13 . The transistor of claim 12 in which at least one p doped region is electrically connected to an n doped region.
14 . The transistor of claim 1 in which said minority carrier trap includes one or more p doped regions and respective closely spaced n doped regions.
15 . A method comprising forming a minority catcher in a substrate, said substrate comprising either the base of a bipolar transistor or a well of a MOS transistor.
16 . The method of claim 15 including the steps of: forming a patterned a resist over said substrate; exposing said substrate to a dopant species; activating said dopant species.