Memory devices and methods of manufacturing the same

1. A vertical memory device, comprising:

a first stack of a plurality of gate electrodes on a substrate, the first stack of the plurality of gate electrodes extending in a first direction that is substantially perpendicular to a top surface of the substrate and ones of the plurality of gate electrodes being stacked along the first direction;

a plurality of channels extending through the first stack of the plurality of gate electrodes along the first direction;

a plurality of charge storage layer structures, each of the plurality of charge storage layer structures being on respective sidewalls of the plurality of channels and including a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern;

a plurality of dummy patterns extending through the first stack of the plurality of gate electrodes in the first direction, ones of the plurality of dummy patterns being enclosed by the first stack of the plurality of the gate electrodes;

a second stack of a plurality of gate electrodes on the substrate, the second stack of the plurality of gate electrodes being spaced apart from the first stack of the plurality of gate electrodes in a second direction that is substantially perpendicular to the first direction; and

a source line in a portion of the substrate that is between the first stack of the plurality of gate electrodes and the second stack of the plurality of gate electrodes.

2. The vertical memory device of claim 1 , wherein ones of the plurality of dummy patterns include silicon oxide, silicon nitride or polysilicon.

3. The vertical memory device of claim 1 , wherein top surfaces of ones of the plurality of dummy patterns have a circular shape, an elliptical shape and/or a polygonal shape.

4. The vertical memory device of claim 1 , wherein top surfaces of ones of the plurality dummy patterns have a linear shape which extends in a third direction that is substantially perpendicular to the first direction.

5. The vertical memory device of claim 1 , wherein ones of the plurality of dummy patterns have a smaller width than a width of ones of the plurality of channels.

6. The vertical memory device of claim 1 , wherein the plurality of dummy patterns comprises:

a first dummy pattern column including first ones of the plurality of dummy patterns disposed along a third direction that is substantially perpendicular to the first direction and the second direction; and

a second dummy pattern column including second ones of the plurality of dummy patterns disposed along the third direction, the first dummy pattern column and the second dummy pattern column being spaced apart from each other in the second direction.

7. The vertical memory device of claim 1 , wherein ones of the plurality of dummy patterns have a top surface that is substantially coplanar with a top surface of ones of the plurality of channels.

8. The vertical memory device of claim 1 , wherein each of the plurality of dummy patterns has a unitary structure.

9. The vertical memory device of claim 8 , wherein the plurality of dummy patterns contacts the first stack of the plurality of gate electrodes.

10. The vertical memory device of claim 1 , further comprising a bit line on the first stack of the plurality of gate electrodes and extending in the second direction, wherein ones of the plurality of the channels and one of the plurality of the dummy patterns are spaced apart along the second direction.

11. A vertical memory device, comprising:

a plurality of channels disposed in a first region of a substrate and extending in a first direction that is substantially perpendicular to a top surface of the substrate;

a plurality of charge storage layer structures, each of the plurality of charge storage layer structures being on respective sidewalls of the plurality of channels;

a stack of a plurality of gate electrodes extending in the first direction, the plurality of gate electrodes being arranged on the sidewalls of the plurality of charge storage layer structures and spaced apart from each other in the first direction;

a plurality of dummy patterns disposed in a second region of the substrate that is adjacent the first region of the substrate, each of the plurality of dummy patterns extending in the first direction and having a smaller width than a width of ones of the plurality of channels, and the plurality of dummy patterns being disposed in and extending through the stack of the plurality of gate electrodes; and

a source line in a portion of the substrate that is adjacent a side of the stack of the plurality of gate electrodes, the source line being spaced apart from the plurality of dummy patterns, wherein the first region of the substrate is between the source line and the second region of the substrate.

12. The vertical memory device of claim 11 , wherein ones of the plurality dummy patterns have a linear shape which extends in a second direction that is substantially perpendicular to the first direction.

13. The vertical memory device of claim 11 , wherein the plurality of dummy patterns comprises:

a first dummy pattern column including a plurality of first dummy patterns formed in a second direction that is substantially perpendicular to the first direction; and

a second dummy pattern column including a plurality of second dummy patterns formed in the second direction and spaced apart from the first dummy pattern column.

14. The vertical memory device of claim 11 , wherein ones of the plurality of dummy patterns have a top surface that is substantially coplanar with a top surface of ones of the plurality of channels.

15. The vertical memory device of claim 11 , wherein each of the plurality of dummy patterns has a unitary structure.

16. The vertical memory device of claim 11 , further comprising a bit line on the plurality of gate electrodes and extending in a second direction that is substantially perpendicular to the first direction, wherein ones of the plurality of the channels and one of the plurality of the dummy patterns are spaced apart along the second direction.

17. A vertical memory device, comprising:

a stack of a plurality of gate electrodes on a substrate, the stack of the plurality of gate electrodes extending in a first direction that is substantially perpendicular to a top surface of the substrate and ones of the plurality of gate electrodes being stacked along the first direction;

a plurality of channels extending through the stack of the plurality of gate electrodes along the first direction;

a plurality of charge storage layer structures, each of the plurality of charge storage layer structures being on respective sidewalls of the plurality of channels and comprising a charge storage layer pattern;

a plurality of dummy patterns extending through the stack of the plurality of gate electrodes in the first direction, each of the plurality of dummy patterns comprising a unitary structure; and

a bit line on the stack of a plurality of gate electrodes, the stack of the plurality of gate electrodes being between the substrate and the bit line, and the plurality of dummy patterns extending through an uppermost one of the plurality of gate electrodes that is closest to the bit line.

18. The vertical memory device of claim 17 , further comprising:

an insulation layer between the uppermost one of the plurality of gate electrodes and the bit line; and

a bit line contact extending through the insulation layer and connecting the bit line to one of the plurality of channels, wherein a lower surface of the insulation layer is coplanar with upper surfaces of the plurality of dummy patterns.

19. The vertical memory device of claim 17 , wherein the bit line extends in a second direction that is substantially perpendicular to the first direction, and

wherein the plurality of the channels and the plurality of the dummy patterns are spaced apart along the second direction.

20. The vertical memory device of claim 17 , further comprising a source line in a portion of the substrate that is adjacent a side of the stack of the plurality of gate electrodes, wherein the plurality of charge storage layer structures are between the source line and the plurality of dummy patterns.