Data processing device
A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
1. A module comprising:
a first substrate;
a semiconductor device mounted over the first substrate;
a first memory device mounted over the first substrate; and
a second memory device mounted over the first substrate,
wherein the semiconductor device includes a semiconductor chip;
wherein the semiconductor chip has a surface, a first memory interface circuit comprised of a first data unit, and a second memory interface circuit comprised of a second data unit;
wherein the surface of the semiconductor chip has a first edge, a second edge facing the first edge, a third edge crossing both the first and second edges, and a fourth edge facing the third edge and crossing both the first and second edges;
wherein the first memory interface circuit is arranged along the first edge of the surface of the semiconductor chip in plan view, and arranged closer to the first edge of the surface of the semiconductor chip than the second edge of the surface of the semiconductor chip in plan view;
wherein a second memory interface circuit is arranged along the third edge of the surface of the semiconductor chip in plan view, and arranged closer to the third edge of the surface of the semiconductor chip than the fourth edge of the surface of the semiconductor chip in plan view;
wherein the first memory device is arranged at the first edge side of the surface of the semiconductor chip in plan view; and
wherein the second memory device is arranged at the third edge side of the surface of the semiconductor chip in plan view.
2. The module according to claim 1 , wherein both the first memory device and the second memory device are comprised of a rectangular shape in plan view;
wherein the first memory device is mounted over the first substrate such that a short side of the first memory device faces the first edge of the surface of the semiconductor chip in plan view; and
wherein the second memory device is mounted over the first substrate such that a short side of the second memory device faces the third edge of the surface of the semiconductor chip in plan view.
3. The module according to claim 1 , wherein both the first memory device and the second memory device are comprised of a rectangular shape in plan view;
wherein the first memory device is mounted over the first substrate such that a long side of the first memory device faces the first edge of the surface of the semiconductor chip in plan view; and
wherein the second memory device is mounted over the first substrate such that a long side of the second memory device faces the third edge of the surface of the semiconductor chip in plan view.
4. The module according to claim 1 , wherein the second data unit of the second memory interface circuit is the same sort as the first data unit of the first memory interface circuit.
5. The module according to claim 1 , wherein the first memory interface circuit is comprised of the first data unit and a first address unit;
wherein the second memory interface circuit is comprised of the second data unit and a second address unit; and
wherein the second address unit of the second memory interface circuit is the same sort as the first address unit of the first memory interface circuit.
6. The module according to claim 5 , wherein in the first memory interface circuit, the first data unit and the first address unit are arranged along the first edge of the surface of the semiconductor chip in series; and
wherein in the second memory interface circuit, the second data unit and the second address unit are arranged along the third edge of the surface of the semiconductor chip in series.
7. The module according to claim 5 , wherein the surface of the semiconductor chip has a first corner crossing the first edge and the third edge, a second corner crossing the first edge and the fourth edge, and a third corner crossing the second edge and the third edge;
wherein in the first memory interface circuit, the first data unit is arranged closer to the first corner of the surface of the semiconductor chip than the first address unit in plan view; and
wherein in the second memory interface circuit, the second data unit is arranged closer to the first corner of the surface of the semiconductor chip than the second address unit in plan view.
8. The module according to claim 1 , wherein the surface of the semiconductor chip has a first corner crossing the first edge and the third edge, a second corner crossing the first edge and the fourth edge, and a third corner crossing the second edge and the third edge;
wherein the first memory interface circuit is arranged closer to the first corner of the surface of the semiconductor chip than the second corner of the surface of the semiconductor chip in plan view; and
wherein the second memory interface circuit is arranged closer to the first corner of the surface of the semiconductor chip than the third corner of the surface of the semiconductor chip in plan view.
9. The module according to claim 1 , wherein the semiconductor device includes a second substrate; and
wherein the semiconductor chip is mounted over the second substrate.
10. The module according to claim 1 , wherein each of the first memory device and the second memory device is SDRAM of Double Data Rate type, which has a pin arrangement in conformity with JEDEC STANDARD.
11. A module comprising:
a first substrate;
a semiconductor device mounted over the first substrate;
a first memory device mounted over the first substrate; and
a second memory device mounted over the first substrate,
wherein the semiconductor device includes a semiconductor chip;
wherein the semiconductor chip has a surface, a first memory interface circuit comprised of a first data unit, a second memory interface circuit comprised of a second data unit, a plurality of first pads formed over the surface and coupled with the first memory interface circuit, and a plurality of second pads formed over the surface and coupled with the second memory interface circuit;
wherein the surface of the semiconductor chip has a first edge, a second edge facing the first edge, a third edge crossing both the first and second edges, and a fourth edge facing the third edge and crossing both the first and second edges;
wherein the first pads are arranged along the first edge of the surface of the semiconductor chip in plan view, and arranged closer to the first edge of the surface of the semiconductor chip than the second edge of the surface of the semiconductor chip in plan view;
wherein the second pads are arranged along the third edge of the surface of the semiconductor chip in plan view, and arranged closer to the third edge of the surface of the semiconductor chip than the fourth edge of the surface of the semiconductor chip in plan view;
wherein the first memory device is arranged at the first edge side of the surface of the semiconductor chip in plan view; and
wherein the second memory device is arranged at the third edge side of the surface of the semiconductor chip in plan view.
12. The module according to claim 11 , wherein both the first memory device and the second memory device are comprised of a rectangular shape in plan view;
wherein the first memory device is mounted over the first substrate such that a short side of the first memory device faces the first edge of the surface of the semiconductor chip in plan view; and
wherein the second memory device is mounted over the first substrate such that a short side of the second memory device faces the third edge of the surface of the semiconductor chip in plan view.
13. The module according to claim 11 , wherein both the first memory device and the second memory device are comprised of a rectangular shape in plan view;
wherein the first memory device is mounted over the first substrate such that a long side of the first memory device faces the first edge of the surface of the semiconductor chip in plan view; and
wherein the second memory device is mounted over the first substrate such that a long side of the second memory device faces the third edge of the surface of the semiconductor chip in plan view.
14. The module according to claim 11 , wherein the second data unit of the second memory interface circuit is the same sort as the first data unit of the first memory interface circuit.
15. The module according to claim 11 , wherein the first memory interface circuit is comprised of the first data unit and a first address unit;
wherein the second memory interface circuit is comprised of the second data unit and a second address unit; and
wherein the second address unit of the second memory interface circuit is the same sort as the first address unit of the first memory interface circuit.
16. The module according to claim 15 , wherein in the first memory interface circuit, the first data unit and the first address unit are arranged along the first edge of the surface of the semiconductor chip in series; and
wherein in the second memory interface circuit, the second data unit and the second address unit are arranged along the third edge of the surface of the semiconductor chip in series.
17. The module according to claim 15 , wherein the surface of the semiconductor chip has a first corner crossing the first edge and the third edge, a second corner crossing the first edge and the fourth edge, and a third corner crossing the second edge and the third edge;
wherein in the first memory interface circuit, the first data unit is arranged closer to the first corner of the surface of the semiconductor chip than the first address unit in plan view; and
wherein in the second memory interface circuit, the second data unit is arranged closer to the first corner of the surface of the semiconductor chip than the second address unit in plan view.
18. The module according to claim 11 , wherein the surface of the semiconductor chip has a first corner crossing the first edge and the third edge, a second corner crossing the first edge and the fourth edge, and a third corner crossing the second edge and the third edge;
wherein the first memory interface circuit is arranged closer to the first corner of the surface of the semiconductor chip than the second corner of the surface of the semiconductor chip in plan view; and
wherein the second memory interface circuit is arranged closer to the first corner of the surface of the semiconductor chip than the third corner of the surface of the semiconductor chip in plan view.
19. The module according to claim 11 , wherein the semiconductor device includes a second substrate; and
wherein the semiconductor chip is mounted over the second substrate.
20. The module according to claim 11 , wherein each of the first memory device and the second memory device is SDRAM of Double Data Rate type, which has a pin arrangement in conformity with JEDEC STANDARD.