Receiver and synchronization correcting method

1. A receiver comprising:

a transformation circuit configured to convert a time domain received signal to a frequency domain signal;

a known signal extraction circuit configured to extract a known signal from the frequency domain signal;

an estimation circuit configured to estimate a channel characteristic based upon the extracted known signal;

a time direction extraction circuit configured to extract channel characteristic values of a particular carrier in a time direction from the estimated channel characteristic;

a power spectrum acquiring circuit configured to acquire a power spectrum from the channel characteristic values extracted in the time direction;

an error calculation circuit configured to calculate a carrier frequency error from the power spectrum; and

a carrier correction circuit configured to correct for a carrier frequency of the received signal based upon the carrier frequency error.

2. The receiver according to claim 1 , further comprising:

a frequency direction extraction circuit configured to extract channel characteristic values of a particular symbol in a frequency direction from the estimated channel characteristic;

a delay profile acquiring circuit configured to acquire a delay profile from the channel characteristic values extracted in the frequency direction;

a delay variation calculation circuit configured to calculate a delay variation of a desired wave contained in the delay profile and determine a clock frequency error based on the delay variation; and

a clock correction circuit configured to perform clock correction on the time domain received signal based upon the clock frequency error.

3. The receiver according to claim 2 , wherein

the delay variation calculation circuit is configured to measure a first delay variation of a first desired wave and a second delay variation of a second desired wave, and calculate the clock frequency error based upon an average value of the first delay variation and the second delay variation if a difference between the first delay variation and the second delay variation is smaller than a predetermined value.

4. The receiver according to claim 3 , wherein

the delay variation calculation circuit is configured to set the clock frequency error to null if the difference between the first delay variation and the second delay variation is at or above the predetermined value.

5. The receiver according to claim 3 , wherein the delay variation calculation circuit is configured to calculate the clock frequency error based upon the first delay variation of the first desired wave if a delay time of the second desired wave cannot be measured and if a delay time of the first desired wave is less than a threshold value.

6. The receiver according to claim 1 , wherein the known signal is a pilot signal scattered in data signals or a transmission control signal of terrestrial digital broadcasting.

7. A receiver comprising:

a transformation circuit configured to convert a time domain received signal to a frequency domain signal;

a known signal extraction circuit configured to extract a known signal from the frequency domain signal;

an estimation circuit configured to estimate a channel characteristic based upon the extracted known signal;

a first frequency direction extraction circuit configured to extract channel characteristic values of a particular symbol at a first extraction interval in a frequency direction from the estimated channel characteristic;

a second frequency direction extraction circuit configured to extract channel characteristic values of said particular symbol at a second extraction interval in the frequency direction from the estimated channel characteristic;

a first delay profile acquiring circuit configured to acquire a first delay profile from the channel characteristic values extracted by the first frequency direction extraction part-circuit;

a second delay profile acquiring circuit configured to acquire a second delay profile from the channel characteristic values extracted by the second frequency direction extraction circuit;

a desired wave delay estimation circuit configured to combine the first delay profile and the second delay profile to acquire a delay time of a desired wave;

a delay variation calculation circuit configured to calculate a delay variation of the desired wave based upon the delay time of the desired wave and determine a clock frequency error based on the delay variation; and

a clock correction circuit configured to perform clock correction on the time domain received signal based upon the clock frequency error.

8. The receiver according to claim 7 , wherein the desired wave delay estimation circuit is configured to determine a position of a fold-back image in the first delay profile based upon a maximum delay time measurable in the first delay profile, and combine the first delay profile having the position of the fold-back image with the second delay profile to determine the delay variation of the desired wave.

9. The receiver according to claim 7 , wherein the known signal is a pilot signal scattered in data signals.

10. The receiver according to claim 7 , wherein the known signal is a transmission control signal of terrestrial digital broadcasting.

11. A synchronization correcting method comprising:

at a receiver, converting a time domain received signal to a frequency domain signal;

extracting a known signal from the frequency domain signal;

estimating a channel characteristic based upon the extracted known signal;

extracting channel characteristic values of a particular carrier in a time direction from the estimated channel characteristic;

acquiring a power spectrum from the channel characteristic values extracted in the time direction;

calculating a carrier frequency error from the power spectrum; and

correcting for a carrier frequency of the time domain received signal based upon the carrier frequency error.

12. The synchronization correcting method according to claim 11 , further comprising:

extracting channel characteristic values of a particular symbol in a frequency direction from the estimated channel characteristic;

acquiring a delay profile from the channel characteristic values extracted in the frequency direction;

calculating a delay variation of a desired wave contained in the delay profile to determine a clock frequency error based on the delay variation; and

performing clock correction on the time domain received signal based upon the clock frequency error.

13. The synchronization correcting method according to claim 12 , wherein the determination of the clock frequency error includes

measuring a first delay variation of a first desired wave in the delay profile and a second delay variation of a second desired wave in the delay profile, and

if a difference between the first delay variation and the second delay variation is smaller than a predetermined value, determining the clock frequency error based upon an average of the first delay variation and the second delay variation.

14. The synchronization correcting method according to claim 13 , wherein the determination of the clock frequency error includes

if the difference between the first delay variation and the second delay variation is at or above the predetermined value, setting the clock frequency error to null.

15. The synchronization correcting method according to claim 13 , wherein the determination of the clock frequency error includes

if a delay time of the second desired wave cannot be measured and if a delay time of the first desired wave is less than a threshold value, calculating the clock frequency error based upon the first delay variation of the first desired wave.

16. The synchronization correcting method according to claim 11 , wherein the known signal is a pilot signal scattered in data signals or a transmission control signal of terrestrial digital broadcasting.