IP Library Granted Patent US 9,206,931
Granted Patent B2
US 9,206,931 · App. 14/183,606 · Granted Dec 8, 2015

Substrate processing apparatus and method of manufacturing semiconductor device

Inventors: Hirohisa Yamazaki (Toyama, JP); Satoshi Okada (Toyama, JP); Tsutomu Kato (Toyama, JP)
Assignee: Hitachi Kokusai Electric Inc.
F16L25/00C23C16/405C23C16/4405C23C16/4408C23C16/45527C23C16/45546H01L21/02271
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Quick Facts
Patent No.
US 9,206,931
App. No.
14/183,606
Granted
Dec 8, 2015
Kind
B2
Abstract

Substrate processing uniformity is improved in the surfaces of wafers and between the wafers. A method of manufacturing a semiconductor device, including: loading a substrate holder into an inner tube, the substrate holder holding a plurality of substrates in a state where the plurality of substrates are horizontally oriented and stacked; forming thin films on the plurality of substrates by supplying a source gas to an inside of the inner tube; and unloading the substrate holder from the inner tube, wherein the forming the thin films is performed in a state where a conductance of a space between an inner wall of the inner tube and a gas penetration preventing cylinder is smaller than a conductance of a region where the plurality of substrates are stacked.

Claims (23)

1. A method of manufacturing a semiconductor device, comprising:

(a) loading a substrate holder into an inner tube, the substrate holder holding a plurality of substrates in a state where the plurality of substrates are horizontally oriented and stacked;

(b) forming thin films on the plurality of substrates by supplying a source gas to an inside of the inner tube; and

(c) unloading the substrate holder from the inner tube,

wherein the step (b) is performed in a state where a conductance of a space between an inner wall of the inner tube and a cylinder disposed under a region where the plurality of substrates are stacked is smaller than a conductance of the region where the plurality of substrates are stacked.

2. A method of claim 1 , wherein the thin films comprise high-k films.

3. A method of manufacturing a semiconductor device, comprising:

(a) loading a substrate holder into an inner tube, the substrate holder holding a plurality of substrates in a state where the plurality of substrates are horizontally oriented and stacked;

(b) forming thin films on the plurality of substrates by supplying a source gas to an inside of the inner tube; and

(c) unloading the substrate holder from the inner tube,

wherein the step (b) is performed in a state where a distance between an outer edge of one of the plurality of substrates accommodated in the inner tube and a gas exhaust outlet is greater than a distance between the outer edge of the one of the plurality of substrates accommodated in the inner tube and a gas injection hole.

4. A method of claim 3 , wherein the thin films comprise high-k films.

5. A method of manufacturing a semiconductor device, comprising:

(a) loading a substrate holder into an inner tube, the substrate holder holding a plurality of substrates in a state where the plurality of substrates are horizontally oriented and stacked;

(b) forming thin films on the plurality of substrates by supplying a source gas to an inside of the inner tube; and

(c) unloading the substrate holder from the inner tube,

wherein the step (b) is performed in a state where a distance between an upper end plate and a top plate of the inner tube is shorter than a distance between a distance between two neighboring substrates of the plurality of substrates.

6. A method of claim 5 , wherein the thin films comprise high-k films.

7. A method of manufacturing a semiconductor device, comprising:

(a) loading a substrate holder into an inner tube, the substrate holder holding a plurality of substrates in a state where the plurality of substrates are horizontally oriented and stacked;

(b) forming thin films on the plurality of substrates by supplying a source gas to an inside of the inner tube; and

(c) unloading the substrate holder from the inner tube,

wherein the step (b) is performed in a state where a conductance of a space between an inner wall of the inner tube and a cylinder disposed under a region where the plurality of substrates are stacked is smaller than a conductance of the region where the plurality of substrates are stacked, and in a state where a distance between an outer edge of one of the plurality of substrates accommodated in the inner tube and a gas exhaust outlet is greater than a distance between the outer edge of the one of the plurality of substrates accommodated in the inner tube and a gas injection hole.

Assignments (1)
CHANGE OF NAME Recorded Nov 26, 2018
From: HITACHI KOKUSAI ELECTRIC INC.
To: KOKUSAI ELECTRIC CORPORATION
Reel/Frame 047620/0001 →
Priority Claims (1)
JP 2008-196562 · Jul 30, 2008 · national
Continuity (2)
Continuation 12510572 · Jul 28, 2009
Related Publication 20140170860A1 · Jun 19, 2014