IP Library Granted Patent US 9,142,544
Granted Patent B2
US 9,142,544 · App. 14/183,737 · Granted Sep 22, 2015

Semiconductor device

Inventor: Kentaro Ikeda (Kanagawa, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/0255H01L25/18H03K17/08148H03K17/12H03K17/127H01L2224/48091H01L2224/48247H01L2224/48464H01L2924/12032H01L2924/13091H01L2924/19105H01L2924/19107
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Quick Facts
Patent No.
US 9,142,544
App. No.
14/183,737
Granted
Sep 22, 2015
Kind
B2
Abstract

A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.

Claims (20)

1. A semiconductor device, comprising:

a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal;

a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate;

a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and

a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.

2. The device according to claim 1 , wherein the normally-on transistor is a GaN-based HEMT.

3. The device according to claim 1 , further comprising a first resistive element with one end electrically connected to the gate terminal and the capacitor and the other end electrically connected to the first gate.

4. The device according to claim 3 , further comprising a second diode provided between the gate terminal and the first gate in parallel with the first resistive element, the second diode having a second anode connected to the gate terminal and a second cathode electrically connected to the first gate.

5. The device according to claim 3 , further comprising a third resistive element having one end electrically connected to the capacitor and the other end electrically connected to the second gate.

6. The device according to claim 1 , further comprising a second resistive element having one end electrically connected to the gate terminal and the other end electrically connected to the capacitor and the first gate.

7. The device according to claim 1 , wherein a capacitance of the capacitor is 10 times or more as large as an input capacitance of the normally-on transistor.

8. The device according to claim 1 , further comprising a Schottky barrier diode having a third anode electrically connected to the first source and a third cathode electrically connected to the first drain and the second source, the Schottky barrier diode having a forward drop voltage lower than a forward drop voltage of a parasitic body diode of the normally-off transistor.

9. The device according to claim 1 , further comprising a Zener diode having a fourth anode electrically connected to the first source and a fourth cathode electrically connected to the first drain and the second source, the Zener diode having a Zener voltage lower than a withstand voltage between the second source and the second gate of the normally-on transistor and lower than an avalanche breakdown voltage of the normally-off transistor.

10. The device according to claim 1 , wherein the normally-off transistor is a Si-vertical MOSFET.

11. The device according to claim 1 , further comprising

a substrate, a source lead wire, a drain lead wire, and a gate lead wire, wherein

the normally-off transistor, the normally-on transistor, the capacitor, and the first diode are mounted on the substrate,

the normally-off transistor and the normally-on transistor are arranged in this order from a side of the source lead wire to a side of the drain lead wire,

the source lead wire is connected to the first source and the first cathode, and

the drain lead wire is connected to the second drain.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2014
From: IKEDA, KENTARO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 032244/0017 →
Priority Claims (1)
JP 2013-058839 · Mar 21, 2013 · national
Continuity (1)
Related Publication 20140284662A1 · Sep 25, 2014