MEMORY DEVICE COMPRISING TILES WITH SHARED READ AND WRITE CIRCUITS

1 . A memory device comprising:

a plurality of simultaneously programmable banks, each bank comprising a plurality of memory tiles, each memory tile divided into a plurality of sub-tiles; and

a multi-level column and a multi-level row select for the plurality of memory tiles.

2 . The memory device of claim 1 , wherein each memory tile is divided into four sub-tiles.

3 . The memory device of claim 2 wherein the multi-level column select is a two level column select comprising a first column select and a second column select.

4 . The memory device of claim 3 , wherein the first column select is a global column select, selecting a memory tile from the plurality of memory tiles.

5 . The memory device of claim 4 , wherein the second column select is a local column select, selecting one or more bitlines in the tile.

6 . The memory device of claim 5 , wherein the multi-level row select is a three-level column select, comprising a first row select, a second row select and a third row select.

7 . The memory device of claim 6 , wherein the first row select selects one of every sixteen rows for a total number of rows in a memory tile.

8 . The memory device of claim 7 , wherein the second row select selects one of every 8 rows from the selected one of every sixteen rows.

9 . The memory device of claim 8 , wherein the third row select selects one row out of every 8 rows for the memory tile.

10 . The memory device of claim 1 , wherein every two tiles share a common wordline.

11 . The memory device of claim 1 , wherein column decoders for each memory tile are separated into even and odd column decoders and placed opposite each other on the memory tile.

12 . The memory device of claim 11 , wherein common source line drivers are separated into even and odd drivers placed opposite each other on the memory tile.

13 . The memory device of claim 12 further comprising a set of redundant memory tiles.