Amplifying circuit

1. An amplifier circuit comprising:

a signal input point;

a control point;

a signal output point; and

a signal amplifying path from the signal input point to the signal output point, the signal amplifying path including a first switch and an amplifier in series with the first switch, a shunting switch for providing a path branching to ground from the amplifying path between the first switch and the amplifier, a capacitor in series between the shunting switch and an input of the amplifier, and a bias circuit connected to a point between the capacitor and the input of the amplifier for providing a bias voltage to the input of the amplifier, the bias voltage level being governed by the control point.

2. An amplifier circuit according to claim 1 , wherein:

the first switch includes a first transistor having a first gate, a first source, and a first drain, the first gate coupled to the control point, one of the first source and first drain coupled to the signal input point and the other of the first source and first drain coupled to the amplifier.

3. An amplifier circuit according to claim 2 , wherein the amplifier includes a second transistor having a second gate, a second source, and a second drain, the second gate coupled to the first switch in the signal amplifying path, and one of the second source and second drain coupled to the signal output point.

4. An amplifier circuit according to claim 3 , wherein the amplifier further includes a third transistor having a third gate, a third source, and a third drain, with one of the third source and third drain coupled to the second transistor and the other of the third source and third drain coupled to the signal output point.

5. An amplifier circuit according to claim 4 , wherein the third transistor is coupled to the signal output point through the second transistor in a cascade amplifying configuration.

6. An amplifier circuit according to claim 2 , further comprising a shunting path branching to ground from the amplifying path between the first switch and the amplifier.

7. An amplifier circuit according to claim 6 , further comprising:

an inverter coupled to the control point, wherein the shunt path includes a shunt path switch coupled to the inverter.

8. An amplifier circuit comprising:

a signal input point;

a signal output point;

a control point;

an isolation transistor including a gate, a source, and a drain;

an amplifying transistor including a gate, a source, and a drain;

a shunting transistor including a gate, a source, and a drain;

a capacitor in series between the shunting transistor and the amplifying transistor; and

a bias circuit connected to a point between the capacitor and the gate of the amplifying transistor for providing a bias voltage to the gate of the amplifying transistor, the bias voltage level being governed by the control point;

wherein:

the isolation transistor gate is coupled to the control point;

one of the source and drain of the isolation transistor is coupled to the signal input point and the other of the source and drain of the isolation transistor is coupled to an amplifying path that is coupled to the gate of the amplifying transistor;

one of the source and drain of the amplifying transistor is coupled to the signal output point and the other of the source and drain of the amplifying transistor is coupled to ground; and

one of the source and drain of the shunting transistor is coupled to the amplifying path and the other of the source and drain of the shunting transistor is coupled to ground.

9. An amplifier circuit according to claim 8 , further comprising a coupling capacitor, wherein said other of the source and drain of the isolation transistor is coupled to the gate of the amplifying transistor through the coupling transistor.

10. An amplifier circuit according to claim 8 , further comprising:

a voltage source; and

an inductor in series with the voltage source,

wherein:

the signal output point is coupled to the voltage source through the inductor.

11. An amplifier circuit according to claim 8 , further comprising a shunting transistor including a gate, a source, and a drain, wherein:

one of the source and drain of the shunting transistor is coupled to one of the source and drain of the isolation transistor; and

the other of the source and drain of the shunting transistor is coupled to ground in a shunting path.

12. An amplifier circuit according to claim 11 , further comprising an inverter having an input coupled to the control point and an output coupled to the gate of the shunting transistor.

13. An amplifier circuit according to claim 8 , further comprising a second amplifying transistor including a gate, a source, and a drain, wherein:

said one of the source and drain of the amplifying transistor is coupled to an output point of the amplifier circuit through the second amplifying transistor in a cascade amplifying configuration.

14. An amplifier circuit according to claim 8 , wherein the isolation transistor attenuates radio-frequency (RF) energy from reaching the gate of the amplifying transistor when the isolation transistor is de-activated.

15. A method of propagating a signal comprising:

receiving a control signal;

receiving a signal at a signal input point of a circuit, the circuit including the signal input point, a signal output point, a signal amplifying path from the signal input point to the signal output point, a shunting path branching from the signal amplifying path to ground, and a bias circuit for providing an input bias voltage to the amplifier, the signal amplifying path including a first switch and an amplifier in series with the first switch, the shunting path including a second switch, the shunting path connecting to the signal amplifying path between the first switch and the amplifier, the signal amplifying path including a capacitor in series between the shunting path an and input to the amplifier, the bias circuit providing the input bias voltage to the signal amplifying path between the capacitor and the input to the amplifier, the bias voltage level being governed by the control signal;

configuring the circuit according to the control signal to assume one of two modes including a signal amplifying mode, and an isolation mode, by which the signal is:

amplified according to the signal amplifying mode by propagating the signal along the signal amplifying path through the first switch, amplifying the signal through the amplifier, and propagating the amplified signal to the signal output point; or

attenuated according to the isolation mode by configuring the first switch to attenuate the signal from propagating along the signal amplifying path and configuring the second switch to shunt the signal to ground along the shunting path.

16. A method according to claim 15 , wherein amplifying the signal through the amplifier comprises propagating the signal from the gate of a first transistor of the amplifier to a source or drain of the first transistor.

17. A method according to claim 16 , wherein amplifying the signal through the amplifier further comprises:

receiving the signal propagated from the source or drain of the first transistor of the amplifier at one of a source and drain of a second transistor of the amplifier; and

further propagating the signal from the other of the source and drain of the second transistor of the amplifier.

18. A method according to claim 15 , wherein:

configuring the first switch to attenuate the signal from propagating along the signal amplifying path comprises receiving the control signal at the first switch; and

configuring the second switch to shunt the signal to ground along the shunting path comprises inverting the control signal and sending the inverted control signal to the second switch.

19. A method according to claim 15 , further comprising:

sending the control signal to one of the first switch and second switch;

inverting the control signal; and

sending the inverted control signal to the other of the first switch and second switch.