III-Nitride Transistor with High Resistivity Substrate
There are disclosed herein various implementations of semiconductor structures including high resistivity substrates. In one exemplary implementation, such a semiconductor structure includes a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm), and a III-N high electron mobility transistor (HEMT) having a drain, a source, and a gate, fabricated over the substrate. The III-N HEMT is configured to produce a two-dimensional electron gas (2 DEG). The resistivity of the substrate reduces the capacitive coupling of the 2 DEG to the substrate. In one implementations, a spatially confined dielectric region is formed in the substrate, under at least one of the drain and the source.
1 . A semiconductor structure comprising:
a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm);
a III-N high electron mobility transistor (HEMT) including a source, a drain, and a gate, fabricated over said substrate, said III-N HEMT configured to produce a two-dimensional electron gas (2 DEG);
a spatially confined dielectric region formed in said substrate, under at least one of said drain and said source.
2 . The semiconductor structure of claim 1 , wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 10 kΩ-cm.
3 . The semiconductor structure of claim 1 , wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 50 kΩ-cm.
4 . The semiconductor structure of claim 1 , wherein said substrate comprises a group IV substrate.
5 . The semiconductor structure of claim 1 , wherein said substrate comprises a silicon substrate.
6 . The semiconductor structure of claim 1 , wherein said spatially confined dielectric region is substantially centered under said at least one of said drain and said source.
7 . The semiconductor structure of claim 1 , wherein all sides of said spatially confined dielectric region are surrounded by said substrate.
8 . The semiconductor structure of claim 1 , wherein a top side of said spatially confined dielectric region is not covered by said substrate.
9 . The semiconductor structure of claim 1 , wherein said spatially confined dielectric region comprises silicon oxide.
10 . The semiconductor structure of claim 1 , wherein said substrate comprises a first substrate layer having said spatially confined dielectric region formed therein, and a second substrate layer situated over said first substrate layer and under said III-N HEMT.
11 . The semiconductor structure of claim 1 , wherein said substrate comprises a plurality of said spatially confined dielectric regions.
12 . A semiconductor structure comprising:
a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm);
a group III-N high electron mobility transistor (HEMT) including a source, a drain, and a gate, fabricated over said substrate;
a spatially confined dielectric region formed in said substrate, under at least one of said drain and said source;
said resistivity of said substrate and said spatially confined dielectric reducing a capacitive coupling of said at least one of said drain and said source to said substrate.
13 . The semiconductor structure of claim 12 , wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 10 kΩ-cm.
14 . The semiconductor structure of claim 12 , wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 50 kΩ-cm.
15 . The semiconductor structure of claim 12 , wherein said substrate comprises a group IV substrate.
16 . The semiconductor structure of claim 12 , wherein said spatially confined dielectric region is substantially centered under said at least one of said drain and said source.
17 . The semiconductor structure of claim 12 , wherein all sides of said spatially confined dielectric region are surrounded by said substrate.
18 . The semiconductor structure of claim 12 , wherein a top side of said spatially confined dielectric region is not covered by said substrate.
19 . The semiconductor structure of claim 12 , wherein said spatially confined dielectric region comprises silicon oxide.
20 . The semiconductor structure of claim 12 , wherein said substrate comprises a first substrate layer having said spatially confined dielectric region formed therein, and a second substrate layer situated over said first substrate layer and under said III-N HEMT.