IP Library › Granted Patent US 9,105,726
Granted Patent B2
US 9,105,726 · App. 14/192,239 · Granted Aug 11, 2015

Transistor and method of fabricating the same

Inventors: Sung Haeng Cho (Chungcheongbuk-do, KR); Sang-Hee Park (Daejeon, KR); Chi-Sun Hwang (Daejeon, KR)
Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
H01L29/786H01L29/41758H01L29/41775H01L29/66742
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,105,726
App. No.
14/192,239
Granted
Aug 11, 2015
Kind
B2
Abstract

Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

Claims (42)

1. A transistor comprising:

a substrate;

a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side;

a first electrode extending along the substrate and contacting the one side of the semiconductor layer;

a second electrode extending along the substrate and contacting the other side of the semiconductor layer;

a conductive wire disposed on the first electrode and spaced from the second electrode;

a gate electrode provided on the semiconductor layer;

a gate insulating layer disposed between the semiconductor layer and the gate electrode, and

an interlayer insulating layer provided directly on the semiconductor layer and covering the gate electrode, wherein the interlayer insulating layer is not vertically over the one side and the other side of the semiconductor layer,

wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar level surface.

2. The transistor of claim 1 , wherein a bottom surface of the semiconductor layer adjacent to the substrate has the same level as a lowermost surface of the first electrode adjacent to the substrate and a lowermost surface of the second electrode adjacent to the substrate.

3. The transistor of claim 1 , wherein the first electrode is disposed at a position facing the second electrode and has a symmetric form to the second electrode.

4. The transistor of claim 1 , wherein the first electrode comprises the same material as the second electrode.

5. The transistor of claim 1 , wherein the semiconductor layer comprises a source region, a drain region, and a channel region,

wherein one of the source region and the drain region extends from the one side and the other one extends from the other side, and the channel region is disposed between the source region and the drain region.

6. The transistor of claim 1 , further comprising a passivation layer covering the conductive wire, the first electrode, the second electrode, and the gate electrode.

7. The transistor of claim 1 , wherein:

the first electrode has a first side near the interlayer insulating layer;

the conductive wire has a second side near the interlayer insulating layer; and

the first side and the second side are coplanar.

8. The transistor of claim 1 , wherein:

the first electrode includes transparent conductive oxides;

the second electrode includes transparent conductive oxides; and

the conductive wire includes at least one of Al and Cu.

9. A transistor comprising:

a substrate;

a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side;

a first electrode extending along the substrate and contacting the one side of the semiconductor layer;

a second electrode extending along the substrate and contacting the other side of the semiconductor layer;

a conductive wire disposed on the first electrode and spaced from the second electrode;

a gate electrode provided on the semiconductor layer;

a gate insulating layer disposed between the semiconductor layer and the gate electrode, and

an interlayer insulating layer provided on the semiconductor layer and covering the gate electrode,

wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar level surface, and

wherein the first electrode is disposed closer to the interlayer insulating layer than the conductive wire is disposed to the interlayer insulating layer.

10. The transistor of claim 9 , wherein the conductive wire does not contact with the interlayer insulating layer.

11. The transistor of claim 9 , wherein the first electrode and the second electrode contact with the interlayer insulating layer.

12. The transistor of claim 9 , wherein the first electrode and the second electrode do not vertically overlap the gate electrode.

13. The transistor of claim 9 , wherein:

the first electrode includes transparent conductive oxides;

the second electrode includes transparent conductive oxides; and

the conductive wire includes at least one of Al and Cu.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: CHO, SUNG HAENG; PARK, SANG-HEE; HWANG, CHI-SUN
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 032315/0543 →
Priority Claims (1)
KR 10-2013-0068263 · Jun 14, 2013 · national
Continuity (1)
Related Publication 20140367689A1 · Dec 18, 2014