IP Library Granted Patent US 9,147,726
Granted Patent B2
US 9,147,726 · App. 14/197,296 · Granted Sep 29, 2015

Semiconductor wafer with a layer of Al

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Quick Facts
Patent No.
US 9,147,726
App. No.
14/197,296
Granted
Sep 29, 2015
Kind
B2
Abstract

A semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) consisting predominantly of silicon and having a (111) surface orientation, a monocrystalline layer (3) of Sc 2 O 3 having a (111) surface orientation, a monocrystalline layer (4) of ScN having a (111) surface orientation, and a monocrystalline layer (6) of Al z Ga 1-z N with 0≦z≦1 having a (0001) surface orientation, the semiconductor wafers are produced by appropriate deposition of the respective layers.

Claims (28)

1. A semiconductor wafer comprising the following layers in the given order:

a) a monocrystalline substrate wafer consisting essentially of silicon and having a (111) surface orientation,

c) a monocrystalline layer of Sc 2 O 3 having a (111) surface orientation,

d) a monocrystalline layer of ScN having a (111) surface orientation, and

f) a monocrystalline layer of Al z Ga 1-z N with 0≦z≦1 having a (0001) surface orientation.

2. The semiconductor wafer of claim 1 , further comprising b), a monocrystalline metal oxide layer between the substrate wafer and the layer of Sc 2 O 3 .

3. The semiconductor wafer of claim 2 , wherein the metal oxide layer has a cubic Ia-3 crystal structure and a composition of (M 1 w M 2 1-w ) 2 O 3 with 0≦w≦1, wherein M 1 is a first metal and M 2 is a second metal, wherein the metal oxide layer is located between the substrate wafer and the layer of Sc 2 O 3 , and wherein M 1 , M 2 and w are selected such that the lattice constant of the metal oxide layer is equal to or smaller than the lattice constant of the substrate wafer and equal to or larger than the lattice constant of the layer of Sc 2 O 3 .

4. The semiconductor wafer of claim 3 , wherein the layer of ScN has a thickness of 2 to 500 nm.

5. The semiconductor wafer of claim 1 , wherein the layer of Sc 2 O 3 has a thickness of 2 to 500 nm.

6. The semiconductor wafer of claim 2 , wherein the layer of Sc 2 O 3 has a thickness of 2 to 500 nm.

7. The semiconductor wafer of claim 1 , wherein the layer of ScN has a thickness of 2 to 500 nm.

8. The semiconductor wafer of claim 2 , wherein the layer of ScN has a thickness of 2 to 500 nm.

9. The semiconductor wafer of claim 1 , further comprising e), a monocrystalline metal nitride layer having a composition of (Al x Ga 1-x ) y Sc 1-y N with 0≦x≦1 and 0<y<1, the metal nitride layer being located between the layer of ScN and the layer of Al z Ga 1-z N.

10. The semiconductor wafer of claim 2 , further comprising e), a monocrystalline metal nitride layer having a composition of (Al x Ga 1-x ) y Sc 1-y N with 0≦x≦1 and 0<y<1, the metal nitride layer being located between the layer of ScN and the layer of Al z Ga 1-z N.

11. The semiconductor wafer of claim 1 , wherein z=0.

12. A process for the production of a semiconductor wafer of claim 1 , comprising the following steps in the given order:

a) providing a substrate wafer,

c) epitaxially depositing a layer of Sc 2 O 3 ,

d) producing a layer of ScN, and

f) epitaxially depositing a layer of Al z Ga 1-z N.

13. The process of claim 12 , wherein a monocrystalline metal oxide layer is epitaxially deposited in an additional step b) after step a) and prior to step c).

14. The process of claim 13 , wherein step c) is performed by means of CVD, MBE, PLD or sputtering techniques.

15. The process of claim 12 , wherein step c) is performed by means of CVD, MBE, PLD or sputtering techniques.

16. The process of claim 12 , wherein in step d) the layer of ScN is produced by converting a surface of the Sc 2 O 3 layer into ScN by exposing the surface to an atmosphere comprising a nitrogen source at a temperature of 200 to 1200° C.

17. The process of claim 12 , wherein in step d) the layer of ScN is produced by depositing a layer of Sc on the surface of the layer of Sc 2 O 3 and subsequently exposing the surface of the layer of Sc to an atmosphere comprising a nitrogen source at a temperature of 200 to 1200° C. and thus converting the layer of Sc into a layer of ScN.

18. The process of claim 12 , wherein in step d) the layer of ScN is produced by epitaxially depositing the layer of ScN on the surface of the layer of Sc 2 O 3 .

19. The process of claim 12 , wherein in a step e), a monocrystalline metal nitride layer having a composition of (Al x Ga 1-x ) y Sc 1-y N with 0≦x≦1 and 0<y<1 is epitaxially deposited after step d) and prior to step f).

20. The process of claim 12 , wherein step f) is performed by means of MOCVD or MBE.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2014
From: THAPA, SARAD BAHADUR; SCHROEDER, THOMAS; TARNAWSKA, LIDIA
To: SILTRONIC AG
Reel/Frame 032350/0942 →