Nonvolatile semiconductor memory device and method of fabricating the same
According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.
1. A nonvolatile semiconductor memory device, comprising:
a first stack unit extending in a first direction, the first direction being in a plane parallel with a substrate, and including first conductive layers stacked above the substrate with first insulating layers interposed between the first conductive layers;
a first semiconductor pillar and a second semiconductor pillar arranged in a second direction crossing the first direction, the second direction being in the plane parallel with the substrate, each of the first semiconductor pillar and the second semiconductor pillar penetrating the first stack unit in a stacking direction and including a first memory layer and a first semiconductor layer, the first memory layer being provided between the first semiconductor layer and one of the first conductive layers; and
second insulating layers provided in first trenches, the first trenches penetrating the first stack unit in the stacking direction, the first trenches being arranged between the first semiconductor pillar and the second semiconductor pillar, the first trenches being arranged at a predetermined interval in the first direction.
2. The device according to claim 1 , wherein
each of the first conductive layers in contact with at least one of the first insulating layers includes a silicide.
3. The device according to claim 1 , wherein
the first trenches are provided in a linear arrangement.
4. The device according to claim 1 , further comprising:
a first select gate layer and a second select gate layer provided above the first stack unit; and
a third insulating layer provided in a second trench, the second trench being provided between the first select gate layer and the second select gate layer, the first select gate layer and the second select gate layer being insulated by the second trench.
5. The device according to claim 1 , further comprising:
a second stack unit extending in the first direction and including second conductive layers stacked above the substrate with fourth insulating layers interposed between the second conductive layers;
a third semiconductor pillar penetrating the second stack unit in the stacking direction and including a second memory layer and a second semiconductor layer, the second memory layer being provided between the second semiconductor layer and one of the second conductive layers; and
a fifth insulating layer provided in a third trench, the third trench being provided between the first stack unit and the second stack unit and extending in the first direction, the first conductive layers and the second conductive layers being insulated by the third trench.
6. The device according to claim 5 , wherein
each of the second conductive layers in contact with the fifth insulating layer includes a silicide.
7. The device according to claim 5 , further comprising:
a third select gate layer provided above the second stack unit; and
a sixth insulating layer provided in a fourth trench, the fourth trench being provided between the second select gate and the third select gate, the sixth insulating layer being in contact with the fifth insulating layer, the second select gate layer and the third select gate layer being insulated by the sixth insulating layer.
8. The device according to claim 5 , further comprising:
a connection semiconductor layer connected to a lower portion of the second semiconductor layer and a lower portion of the third semiconductor layer; and
a back gate layer provided on the connection semiconductor layer via a seventh insulating layer.
9. The device according to claim 8 , wherein
a first memory string is composed of the second semiconductor pillar, the third semiconductor pillar, and the first connection portion.
10. The device according to claim 5 , further comprising:
a fourth semiconductor pillar penetrating the second stack unit in the stacking direction and including a third memory portion and a third semiconductor layer, the third memory being provided between the third semiconductor layer and one of the second conductive layer, the third semiconductor pillar and the fourth semiconductor pillar being arranged in the second direction; and
eighth insulating layers provided in fifth trenches, the fifth trenches penetrating the second stack unit in the stacking direction, the fifth trenches being arranged between the third semiconductor pillar and the fourth semiconductor pillar, the fifth trenches being arranged at predetermined interval in the first direction.
11. The device according to claim 10 , wherein
locations of the second insulating layers are shifted from locations of the eighth insulating layers in the first direction.
12. The device according to claim 5 , further comprising:
a wiring electrically connected to an upper portion of the second semiconductor layer and an upper portion of the third semiconductor layer.
13. The device according to claim 1 , wherein
the first stack unit has a stripe shape extending in the first direction.
14. The device according to claim 5 , wherein
the third trench has a stripe shape extending in the first direction.