Conformal nitridation of one or more fin-type transistor layers
Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
1. A method comprising:
fabricating a fin-type transistor structure, the fabricating comprising:
forming at least one material layer disposed conformally over a fin extending above a substrate, the at least one material layer comprising a gate dielectric layer with an exposed surface; and
performing a conformal nitridation process on the exposed surface of the pre-formed gate dielectric layer, the conformal nitridation process forming an exposed, conformal nitrided surface with an increased nitrogen concentration as compared to an underlying portion of the gate dielectric layer.
2. The method of claim 1 , wherein performing the conformal nitridation process comprises performing a plasma nitridation of the exposed surface of the gate dielectric layer.
3. The method of claim 2 , wherein performing the conformal nitridation process further comprises performing a flash annealing process over the gate dielectric layer, prior to performing the plasma nitridation over the gate dielectric layer, the flash annealing process facilitating removing one or more oxygen voids within the gate dielectric layer.
4. The method of claim 3 , wherein the flash annealing process comprises an oxygen flash annealing process.
5. The method of claim 1 , wherein the at least one material layer is multiple material layers, the multiple material layers being conformally disposed, at least in part, over the fin extending above the substrate, and comprising a capping layer disposed above the gate dielectric layer.
6. The method of claim 5 , wherein performing the conformal nitridation process comprises performing the conformal nitridation process over the gate dielectric layer, prior to providing the capping layer over the gate dielectric layer.
7. The method of claim 5 , further comprising performing a second plasma nitridation over an exposed surface of the capping layer.
8. The method of claim 7 , wherein the second plasma nitridation forms an exposed, conformal nitrided surface for the capping layer, and the method further comprises performing a post annealing process, subsequent to the second plasma nitridation, to at least partially diffuse nitrogen into the capping layer, the at least partially diffused nitrogen forming a nitrided region within an upper portion of the capping layer.
9. The method of claim 5 , wherein the gate dielectric layer comprises an oxide material and the capping layer comprises a nitride material.
10. The method of claim 1 , wherein the method further comprises performing a post annealing process, subsequent to the plasma nitridation of the gate dielectric layer, to at least partially diffuse nitrogen from the exposed, conformal oxynitrided surface into the underlying portion of the gate dielectric layer, the at least partially diffused nitrogen in the upper portion of the gate dielectric layer forming a oxynitrided region within an upper portion of the gate dielectric layer.
11. The method of claim 10 , wherein the post annealing process increases the concentration of nitrogen within conformal, oxynitrided surface of the gate dielectric layer.
12. The method of claim 1 , wherein the plasma nitridation process is performed in the presence of a gaseous plasma material to form the exposed, conformal nitride surface.
13. The method of claim 12 , wherein the gaseous plasma material comprises at least one of nitrogen gas or ammonia gas.
14. The method of claim 12 , wherein the plasma nitridation process is performed at a temperature within a range of about 350° C. to 400° C.
15. The method of claim 1 , wherein performing the conformal nitridation process further comprises performing a post annealing process, subsequent to performing the plasma nitridation, to at least partially diffuse nitrogen from the exposed, conformal nitrided surface into the underlying portion of the gate dielectric layer.
16. The method of claim 15 , wherein the post annealing process comprises performing at least one of a rapid-thermal (RTA) annealing process, a spike annealing process or a minute second process over the exposed, conformal nitrided surface.
17. The method of claim 1 , wherein the at least one material layer is formed via a process that differs from the conformal nitridation process.
18. The method of claim 1 , wherein the at least one material layer is formed via at least one deposition process selected form the group consisting of atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD) and plasma-enhanced CVD (PECVD).