Thermal vias disposed in a substrate proximate to a well thereof

1. An apparatus, comprising:

a three-dimensional stacked integrated circuit having at least a first die and a second die interconnected to one another using die-to-die interconnects;

wherein a substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate;

wherein a first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom;

wherein the substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate;

wherein a second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity;

wherein the substrate is a semiconductor-on-insulator substrate having a buried dielectric layer; and

wherein the first end stops on the buried dielectric layer of the substrate.

2. The apparatus according to claim 1 , further comprising:

a pad associated with the upper surface of the substrate;

wherein the at least one thermal via structure is a plurality of thermal via structures;

wherein widths of the plurality of thermal via structures are each less than a width of the through substrate via structure to etch the plurality of thermal via structures and the at least one through substrate via structure at the same time; and

wherein the pad is an etch stop layer for the at least one through substrate via structure.

3. The apparatus according to claim 2 , wherein the widths of the plurality of thermal via structures are in a range of approximately 0.5 to 100 microns.

4. The apparatus according to claim 3 , wherein:

the plurality of thermal via structures are in a high-density array with a pitch in a range of approximately 1 to 200 microns; and

the width of the at least one through substrate via structure is in a range of approximately 1 to 5 times any of the widths of the plurality of thermal via structures.

5. The apparatus according to claim 1 , wherein depth of the at least one thermal via structure is approximately 1 to 200 microns which is approximately 1 to 20 microns less than depth of the at least one through substrate via structure.

6. The apparatus according to claim 1 , wherein the at least one through substrate via structure is a signal via structure.

7. The apparatus according to claim 1 , wherein the at least one through substrate via structure is a thermal via structure.

8. The apparatus according to claim 1 , wherein the first end is within 20 microns inclusive of the well.

9. The apparatus according to claim 1 , wherein the buried dielectric layer is of a partial silicon-on-insulator wafer.

10. The apparatus according to claim 1 , wherein the at least one through substrate via structure extends through the buried dielectric layer.

11. The apparatus according to claim 10 , wherein the at least one through substrate via structure extends through a gap between dielectric islands of the buried dielectric layer.

12. An apparatus, comprising:

a substrate having a plurality of thermal via structures extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate;

first ends of the plurality of thermal via structures are at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom;

the substrate has a through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate;

second ends of the plurality of thermal via structures are coupled to a heat sink;

wherein the substrate is a semiconductor-on-insulator substrate having a buried dielectric layer; and

wherein the first ends stop on the buried dielectric layer of the substrate.

13. The apparatus according to claim 12 , wherein an air gap is located between sidewalls of the plurality of thermal via structures and the substrate to provide fins.

14. A method, comprising:

forming a patterned masking layer on a surface of a substrate;

wherein the substrate has thereon a stack of inter-dielectric layers and metal layers on an opposite surface with respect to the surface of the substrate;

etching vias in the substrate through openings in the patterned masking layer;

wherein the vias extend from the surface toward a well of the substrate without extending to the well and without extending through the substrate;

wherein ends of the vias are at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom;

plating the vias to provide thermal via structures;

wherein the etching is for forming a portion of a through substrate via; and

wherein the ends of the vias are provided by a surface of a buried dielectric layer of the substrate.

15. The method according to claim 14 , wherein:

the etching is further for forming another through substrate via; and

the etching for the other through substrate via extends from the surface of the substrate to the opposite surface of the substrate.

16. The method according to claim 14 ,

further comprising:

masking the vias; and

etching a hole in the buried dielectric layer to extend the through substrate via.

17. The method according to claim 16 , further comprising:

continuing the etching after forming the hole in the buried dielectric layer down to a conductive pad;

wherein the plating is of the vias as well as the through substrate via to provide the thermal via structures and a signal via structure, respectively.

18. The method according to claim 16 , wherein the substrate is selected from a group consisting of a semiconductor-on-insulator substrate and a partial semiconductor-on-insulator substrate.

19. The method according to claim 14 , wherein the substrate is of a first die, the method further comprising:

interconnecting ends of the thermal via structures to a second die;

wherein at least a portion of the thermal via structures are coupled to at least one through die via structure of the second die for thermal conductivity.