Patent Assignment
Reel/Frame 073508/0668
Change of Name
Recorded: 2025-11-24
Pages: 8
Assignor
INVENSAS CORPORATION
Executed: 2021-10-01
Assignee
INVENSAS LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(90)
Inverted Optical Device
Off Substrate Kinking of Bond Wire
Warpage Reduction in Structures with Electircal Circuitry
Thermal Vias Disposed in a Substrate Without a Liner Layer
Thermal Vias Disposed in a Substrate Proximate to a Well Thereof
Making Electrical Components in Handle Wafers of Integrated Circuit Packages
Conductive Connections, Structures with Such Connections, and Methods of Manufacture
Conductive Connections, Structures with Such Connections, and Methods of Manufacture
Compact Semiconductor Package and Related Methods
Integrated Circuit Assemblies with Reinforcement Frames, and Methods of Manufacture
Structure and Method for Integrated Circuits Packaging with Increased Density
Low Cte Component with Wire Bond Interconnects
Wire Bond Support Structure and Microelectronic Package Including Wire Bonds Therefrom
Severing Bond Wire by Kinking and Twisting
Making Multilayer 3D Capacitors Using Arrays of Upstanding Rods or Ridges
Microelectronic Assemblies with Integrated Circuits and Interposers with Cavities, and Methods of Manufacture
Die Stacking Techniques in Bga Memory Package for Small Footprint Cpu and Memory Motherboard Design
Device and Method for Localized Underfill
Paddle for Materials Processing
Use of Underfill Tape in Microelectronic Components, and Microelectronic Components with Cavities Coupled to Through-Substrate Vias
Polymer Member Based Interconnect
Bga Ballout Partition Techniques for Simplified Layout in Motherboard with Multiple Power Supply Rail
Holding of Interposers and Other Microelectronic Workpieces in Position During Assembly and Other Processing
Interposers with Circuit Modules Encapsulated by Moldable Material in a Cavity, and Methods of Fabrication
Bond Via Array for Thermal Conductivity
Integrated Interposer Solutions for 2D and 3D Ic Packaging
Method for Fabricating Interconnection Circuitry with Electricall Conductive Features Passing Through a Support and Comprising Core Portions Formed Using Nanoparticle-Containing Inks
Localized sealing of interconnect structures in small gaps
Patent:
9,331,043 →
Application:
14/609,720 →
Contact Arrangements for Stackable Microelectronic Package Structures
Patent:
9,337,170 →
Application:
14/609,878 →
Contact Arrangements for Stackable Microelectronic Package Structures with Multiple Ranks
Patent:
9,349,707 →
Application:
14/609,896 →
Microelectronic Assemblies Formed Using Metal Silicide, and Methods of Fabrication
Microelectronic Components with Features Wrapping Around Protrusions of Conductive Vias Protruding from Through-Holes Passing Through Substrates
Patent:
9,397,038 →
Application:
14/633,746 →
Pressing of Wire Bond Wire Tips to Provide Bent-Over Tips
Embedded Graphite Heat Spreader for 3DIC
High Performance Compliant Substrate
Coupling of Side Surface Contacts to a Circuit Platform
Wafer-Level Packaging Using Wire Bond Wires in Place of a Redistribution Layer
Microelectronic Assemblies with Cavities, and Methods of Fabrication
Patent:
9,478,504 →
Application:
14/745,237 →
Structures and Methods for Low Temperature Bonding Using Nanoparticles
Wafer Level Packages with Mechanically Decoupled Fan-in and Fan-Out Areas
Patent:
9,543,277 →
Application:
14/830,973 →
Making Electrical Components in Handle Wafers of Integrated Circuit Packages
Semiconductor Packages and Other Circuit Modules with Porous and Non-Porous Stabilizing Layers
Fan-Out Wafer-Level Packaging Using Metal Foil Lamination
Microelectronic Assemblies with Integrated Circuits and Interposers with Cavities, and Methods of Manufacture
Interposers with Circuit Modules Encapsulated by Moldable Material in a Cavity, and Methods of Fabrication
Compact Semiconductor Package and Related Methods
Thermal vias disposed in a substrate without a liner layer
Inverted Optical Device
Off Substrate Kinking of Bond Wire
Localized sealing of interconnect structures in small gaps
Device and Method for Localized Underfill
Polymer Member Based Interconnect
Integrated Circuit Assemblies with Reinforcement Frames, and Methods of Manufacture
Thermal Vias Disposed in a Substrate Proximate to a Well Thereof
Warpage Reduction in Structures with Electrical Circuitry
Circuit Assemblies with Multiple Interposer Substrates, and Methods of Fabrication
Microelectronic Components with Features Wrapping Around Protrusions of Conductive Vias Protruding from Through-Holes Passing Through Substrates
Microelectronic Assemblies Formed Using Metal Silicide, and Methods of Fabrication
Making Multilayer 3D Capacitors Using Arrays of Upstanding Rods or Ridges
Wire Bond Support Structure and Microelectronic Package Including Wire Bonds Therefrom
Conductive Connections, Structures with Such Connections, and Methods of Manufacture
Integrated Circuits Protected by Substrates with Cavities, and Methods of Manufacture
Microelectronic Assemblies with Cavities, and Methods of Fabrication
Wafer-Level Packaging Using Wire Bond Wires in Place of a Redistribution Layer
Compact Semiconductor Package and Related Methods
Making Electrical Components in Handle Wafers of Integrated Circuit Packages
Integrated Circuit Assemblies with Rigid Layers Used for Protection Against Mechanical Thinning and for Other Purposes, and Methods of Fabricating Such Assemblies
Fan-Out Wafer-Level Packaging Using Metal Foil Lamination
Structures and Methods for Low Temperature Bonding Using Nanoparticles
Light Emitting Diode Device with Reconstituted Led Components on Substrate
Method for Reduced Load Memory Module
Low Cte Component with Wire Bond Interconnects
High Performance Compliant Substrate
Microelectronic Components with Features Wrapping Around Protrusions of Conductive Vias Protruding from Through-Holes Passing Through Substrates
Integrated Interposer Solutions for 2D and 3D Ic Packaging
Interposers with Electrically Conductive Features Having Different Porosities
Conductive Connections, Structures with Such Connections, and Methods of Manufacture
Making Electrical Components in Handle Wafers of Integrated Circuit Packages
Tall and Fine Pitch Interconnects
Contact Structures with Porous Networks for Solder Connections, and Methods of Fabricating Same
Integrated Circuits Protected by Substrates with Cavities, and Methods of Manufacture
Pressing of Wire Bond Wire Tips to Provide Bent-Over Tips
Embedded Graphite Heat Spreader for 3DIC
Microelectronic Components with Features Wrapping Around Protrusions of Conductive Vias Protruding from Through-Holes Passing Through Substrates
Low Cte Component with Wire Bond Interconnects
Tall and Fine Pitch Interconnects
Microelectronic Components with Features Wrapping Around Protrusions of Conductive Vias Protruding from Through-Holes Passing Through Substrates
Making Electrical Components in Handle Wafers of Integrated Circuit Packages
Integrated Interposer Solutions for 2D and 3D Ic Packaging
Contact Structures with Porous Networks for Solder Connections, and Methods of Fabricating Same
Related Assignments
(21)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 18, 2011
From: MOHAMMED, ILYAS; BEROZ, MASUD; WANG, LIANG
To: INVENSAS CORPORATION
Reel/Frame 027252/0681 →
Assignment of Assignor's Interest
Nov 12, 2013
From: HABA, BELGACEM; CO, REYNALDO; CIZEK, RIZZA LEE SAGA; ZOHNI, WAEL
To: INVENSAS CORPORATION
Reel/Frame 031587/0172 →
Assignment of Assignor's Interest
Dec 4, 2013
From: UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 031765/0407 →
Assignment of Assignor's Interest
Mar 7, 2014
From: GAO, GUILIAN
To: INVENSAS CORPORATION
Reel/Frame 032383/0061 →
Assignment of Assignor's Interest
Mar 7, 2014
From: KATKAR, RAJESH; ARKALGUD, SITARAM; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 032383/0420 →
Assignment of Assignor's Interest
May 2, 2014
From: WANG, LIANG; SHEN, HONG; KATKAR, RAJESH
To: INVENSAS CORPORATION
Reel/Frame 032814/0762 →
Assignment of Assignor's Interest
May 13, 2014
From: UZOH, CYPRIAN EMEKA; KATKAR, RAJESH
To: INVENSAS CORPORATION
Reel/Frame 032878/0311 →
Assignment of Assignor's Interest
May 13, 2014
From: KATKAR, RAJESH; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 032878/0431 →
Assignment of Assignor's Interest
May 22, 2014
From: UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 032952/0605 →
Assignment of Assignor's Interest
May 27, 2014
From: KATKAR, RAJESH; MIRKARIMI, LAURA WILLS; SITARAM, ARKALGUD R.; WOYCHIK, CHARLES G.
To: INVENSAS CORPORATION
Reel/Frame 032969/0801 →
Assignment of Assignor's Interest
Jun 2, 2014
From: KATKAR, RAJESH; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 033011/0480 →
Assignment of Assignor's Interest
Jul 10, 2014
From: SHEN, HONG; WOYCHIK, CHARLES G.; SITARAM, ARKALGUD R.
To: INVENSAS CORPORATION
Reel/Frame 033290/0364 →
Assignment of Assignor's Interest
Jul 21, 2014
From: HABA, BELGACEM; CO, REYNALDO; CIZEK, RIZZA LEE SAGA; ZOHNI, WAEL
To: INVENSAS CORPORATION
Reel/Frame 033356/0217 →
Assignment of Assignor's Interest
Jul 31, 2014
From: SUN, ZHUOWEN; CHEN, YONG; BANG, KYONG-MO
To: INVENSAS CORPORATION
Reel/Frame 033438/0415 →
Assignment of Assignor's Interest
Nov 4, 2014
From: WANG, LIANG; KATKAR, RAJESH; SHEN, HONG; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 034096/0597 →
Assignment of Assignor's Interest
Mar 26, 2015
From: WOYCHIK, CHARLES G.; SITARAM, ARKALGUD R.; CAO, ANDREW; LEE, BONG-SUB
To: INVENSAS CORPORATION
Reel/Frame 035268/0944 →
Assignment of Assignor's Interest
May 27, 2015
From: CO, REYNALDO; ZOHNI, WAEL; CIZEK, RIZZA LEE SAGA; KATKAR, RAJESH
To: INVENSAS CORPORATION
Reel/Frame 035725/0555 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name
Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →