IP Library Granted Patent US 9,412,806
Granted Patent B2
US 9,412,806 · App. 14/304,535 · Granted Aug 9, 2016

Making multilayer 3D capacitors using arrays of upstanding rods or ridges

Inventors: Liang Wang (Milpitas, CA); Rajesh Katkar (San Jose, CA); Hong Shen (Oak Park, CA); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: Invensas Corporation
H01L28/90H01L28/65
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Quick Facts
Patent No.
US 9,412,806
App. No.
14/304,535
Granted
Aug 9, 2016
Kind
B2
Abstract

In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Claims (41)

1. A method for making a capacitor, the method comprising:

providing a substrate having a surface;

depositing a first electroconductive layer on the surface;

bonding an end of at least one upstanding wire to the first electroconductive layer by a first bond comprising at least one of a molten ball bond and an ultrasonic bond;

coating the first electroconductive layer and the at least one wire with a dielectric layer, which comprises at least part of capacitor dielectric for the capacitor; and

depositing a second electroconductive layer on the dielectric layer, the second electroconductive layer comprising at least part of a first capacitor electrode for the capacitor.

2. The method of claim 1 , wherein the bonding comprises bonding respective ends of an array of upstanding wires to the first electroconductive layer.

3. The method of claim 1 , wherein the at least one wire comprises gold (Au), copper (Cu) or aluminum (Al).

4. The method of claim 1 , wherein the first bond comprises a stitch bond.

5. The method of claim 1 , wherein the first bond comprises a molten ball bond.

6. The method of claim 1 wherein the at least one wire comprises at least part of a second capacitor electrode for the capacitor.

7. The method of claim 1 wherein said bonding comprises, for the at least one wire:

providing a supply of wire in a bonding tool, the supply of wire comprising the at least one wire exposed at an opening of a capillary of the bonding tool;

bonding the at least one wire to the first electroconductive layer; and

severing the at least one wire from the supply of wire.

8. A method for making a capacitor, the method comprising:

providing a substrate having a surface;

depositing a first electroconductive layer on the surface;

bonding an end of at least one upstanding wire to the first electroconductive layer;

coating the first electroconductive layer and the at least one wire with a dielectric layer; and

depositing a second electroconductive layer on the dielectric layer;

wherein the at least one wire comprises gold (Au), copper (Cu) or aluminum (Al); and

wherein the at least one wire is plated with palladium (Pd).

9. A structure comprising:

a surface;

one or more first structures located on the surface, each first structure extending away from the surface, each first structure comprising:

a wire bonded to the surface by a first bond comprising at least one of a molten ball bond and a stitch bond;

one or more dielectric features covering the wire, each dielectric feature comprising at least part of a capacitor dielectric for a capacitor; and

one or more electroconductive layers each of which overlies at least one said dielectric layer and comprises at least part of a first capacitor electrode for the capacitor.

10. The structure of claim 9 , wherein in at least one said first structure, the wire is bonded to the surface by the respective first bond comprising the stitch bond.

11. The structure of claim 9 , wherein in at least one said first structure, the wire is bonded to the surface by the respective first bond comprising the molten ball bond.

12. The structure of claim 9 wherein in at least one said first structure, the wire comprises at least part of a second capacitor electrode for the capacitor.

13. The structure of claim 9 wherein the one or more first structures are a plurality of first structures.

14. A method for making a capacitor, the method comprising:

providing a first electroconductive layer;

providing a supply of wire comprising a portion exposed at an opening of a capillary of a bonding tool;

bonding the portion of the supply of wire to the first electroconductive layer to form a bond between the supply of wire and the first electroconductive layer;

severing a length of wire from the supply of wire, the length of wire being a wire bonded to the first electroconductive layer by the bond and comprising a longitudinal segment extending away from the bond and away from the first electroconductive layer;

coating the longitudinal segment with a dielectric which comprises at least part of a capacitor dielectric for the capacitor; and

coating the dielectric with a second electroconductive layer, the second electroconductive layer comprising at least part of a first capacitor electrode for the capacitor.

15. The method of claim 14 wherein the wire comprises at least part of a second capacitor electrode for the capacitor.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0668 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2014
From: WANG, LIANG; KATKAR, RAJESH; SHEN, HONG; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 034096/0597 →
Continuity (1)
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