Contact arrangements for stackable microelectronic package structures

1. A microelectronic assembly, comprising:

a first substrate having a first and a second surface on opposite sides of the first substrate; and

a plurality of contact arrangements disposed on the first surface of the first substrate;

wherein the plurality of contact arrangements comprises:

first contacts disposed as a first ring array of the plurality of contact arrangements on the first surface;

second contacts disposed interior to the first contacts as a second ring array of the plurality of contact arrangements on the first surface;

third contacts disposed interior to the second contacts as a third ring array of the plurality of contact arrangements on the first surface;

fourth contacts disposed interior to the third contacts on the first surface as an innermost array of the plurality of contact arrangements on the first surface;

wherein the first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a first central region of the concentric rings;

wherein the first contacts and the fourth contacts are for interconnection with first microelectronic dies; and

wherein the second contacts and the third contacts are for interconnection with second microelectronic dies.

2. The microelectronic assembly according to claim 1 , further comprising:

a second substrate having a third and a fourth surface on opposite sides of the second substrate;

wherein the first contacts and the fourth contacts are respectively interconnected to first stack wires and second stack wires for interconnection with the third surface of the second substrate.

3. The microelectronic assembly according to claim 2 , wherein:

the first stack wires and the second stack wires extend from the second surface of the first substrate to the third surface of the second substrate;

the second surface and the third surface define an interior region therebetween for the second microelectronic dies; and

the first stack wires and the second stack wires are for interconnection with the first microelectronic dies disposed above the fourth surface.

4. The microelectronic assembly according to claim 2 , wherein:

the second contacts and the third contacts are respectively for interconnecting to the second microelectronic dies disposed above the second surface; and

the second contacts and the third contacts are for interconnection with the second microelectronic dies in same a package as the first microelectronic dies.

5. The microelectronic assembly according to claim 3 , wherein the third contacts and the fourth contacts are control and address signal contacts for the second microelectronic dies and the first microelectronic dies, respectively.

6. The microelectronic assembly according to claim 5 , wherein the first contacts and the second contacts are data signal contacts for the first microelectronic dies and the second microelectronic dies, respectively.

7. The microelectronic assembly according to claim 1 , wherein the first microelectronic dies include:

a first memory die and a second memory die spaced apart from one another with each in a latitudinal orientation; and

a third memory die and a fourth memory die spaced apart from one another with each in a longitudinal orientation;

wherein the first memory die, the second memory die, the third memory die, and the fourth memory die of each of the first microelectronic dies define a respective second central region.

8. The microelectronic assembly according to claim 1 , wherein the first microelectronic dies and the second microelectronic dies are of a memory module having a single rank and at least two channels.

9. A microelectronic assembly, comprising:

a first substrate having a first and a second surface on opposite sides of the first substrate; and

a plurality of contact arrangements disposed on the first surface of the first substrate;

wherein the plurality of contact arrangements comprises:

first contacts disposed as a first block and a first L-shaped region spaced apart from one another in a first quadrant of the plurality of contact arrangements on the first surface;

second contacts disposed as a second block and a second L-shaped region spaced apart from one another in a second quadrant of the plurality of contact arrangements on the first surface;

third contacts disposed as a third block and a third L-shaped region spaced apart from one another in a third quadrant of the plurality of contact arrangements on the first surface; and

fourth contacts disposed as a fourth block and a fourth L-shaped region spaced apart from one another in a fourth quadrant of the plurality of contact arrangements on the first surface;

wherein the first contacts and the fourth contacts are for interconnection with first microelectronic dies; and

wherein the second contacts and the third contacts are for interconnection with second microelectronic dies.

10. The microelectronic assembly according to claim 9 , wherein:

the first L-shaped region, the second L-shaped region, the third L-shaped region, and the fourth L-shaped are respective corners of a quadrilateral defining a first central region having disposed therein the first block, the second block, the third block, and the fourth block;

the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant of the quadrilateral are each spaced apart from one another;

the first L-shaped region and the fourth L-shaped region are diagonally opposed to one another;

the second L-shaped region and the third L-shaped region are diagonally opposed to one another;

the first block and the fourth block are diagonally opposed to one another; and

the second block and the third block are diagonally opposed to one another.

11. The microelectronic assembly according to claim 9 , further comprising:

a second substrate having a third and a fourth surface on opposite sides of the second substrate;

wherein:

the first contacts of the first block and the first L-shaped region are respectively interconnected to a first set and a second set of stack wires;

the fourth contacts of the fourth block and the fourth L-shaped region are respectively interconnected to a third set and a fourth set of the stack wires;

the stack wires extend from the second surface of the first substrate for interconnecting to the third surface of the second substrate; and

the second surface and the third surface define an interior region therebetween for locating the second microelectronic dies.

12. The microelectronic assembly according to claim 11 , wherein the stack wires are for interconnection to the first microelectronic dies disposed above the fourth surface.

13. The microelectronic assembly according to claim 12 , wherein:

the second contacts and the third contacts are respectively interconnected to the second microelectronic dies disposed above the second surface; and

wherein the second contacts and the third contacts are for interconnection with the second microelectronic dies in same a package as the first microelectronic dies.

14. The microelectronic assembly according to claim 11 , wherein:

the first contacts of the first block and the fourth contacts of the fourth block are first control and address signal contacts for the first microelectronic dies; and

the second contacts of the second block and the third contacts of the third block are second control and address signal contacts for the second microelectronic dies.

15. The microelectronic assembly according to claim 14 , wherein

the first contacts of the first L-shaped region and the fourth contacts of the fourth L-shaped region are first data signal contacts for the first microelectronic dies; and

the second contacts of the second L-shaped region and the third contacts of the third L-shaped region are second data signal contacts for the second microelectronic dies.

16. The microelectronic assembly according to claim 9 , wherein the first microelectronic dies include:

a first memory die and a second memory die spaced apart from one another with each in a latitudinal orientation;

a third memory die and a fourth memory die spaced apart from one another with each in a longitudinal orientation; and

the first memory die, the second memory die, the third memory die, and the fourth memory die define a second central region.

17. The microelectronic assembly according to claim 9 , wherein the first microelectronic dies and the second microelectronic dies are of a memory module having a single rank and at least two channels.

18. A method for forming a microelectronic assembly, comprising:

obtaining a first substrate having a first surface and a second surface on opposite sides of the first substrate;

forming a plurality of contact arrangements on the first surface of the first substrate;

wherein the plurality of contact arrangements comprises:

first contacts disposed as a first ring array of the plurality of contact arrangements on the first surface;

second contacts disposed interior to the first contacts as a second ring array of the plurality of contact arrangements on the first surface;

third contacts disposed interior to the second contacts as a third ring array of the plurality of contact arrangements on the first surface;

fourth contacts disposed interior to the third contacts on the first surface;

wherein the first ring array, the second ring array, and the third ring array are concentric rings with the fourth contacts in a central region of the concentric rings;

wherein the first contacts and the fourth contacts are for interconnection with first microelectronic dies; and

wherein the second contacts and the third contacts are for interconnection with second microelectronic dies in same a package as the first microelectronic dies.

19. The method according to claim 18 , further comprising:

obtaining a second substrate having a third and a fourth surface on opposite sides of the second substrate; and

interconnecting the first contacts and the fourth contacts respectively to first stack wires and second stack wires;

wherein the first stack wires and the second stack wires extend from the second surface of the first substrate for interconnecting to the third surface of the second substrate;

wherein the second surface and the third surface define an interior region therebetween for the second microelectronic dies disposed above the second surface.

20. The method according to claim 19 , further comprising:

interconnecting the second contacts and the third contacts respectively to the second microelectronic dies disposed above the second surface; and

interconnecting the first stack wires and the second stack wires to the first microelectronic dies disposed above the fourth surface.