IP Library Granted Patent US 9,865,675
Granted Patent B2
US 9,865,675 · App. 15/207,837 · Granted Jan 9, 2018

Making multilayer 3D capacitors using arrays of upstanding rods or ridges

Inventors: Liang Wang (Milpitas, CA); Rajesh Katkar (San Jose, CA); Hong Shen (Palo Alto, CA); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: INVENSAS CORPORATION
H01L28/65H01L28/90H01L28/92H01L2224/16145H01L2224/16225H01L2924/15153H01L2924/15184H01L2924/15192H01L2924/16151H01L2924/16152H01L2924/16195H01L2924/181
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Quick Facts
Patent No.
US 9,865,675
App. No.
15/207,837
Granted
Jan 9, 2018
Kind
B2
Abstract

In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Claims (31)

1. A method for making a capacitor, the method comprising:

providing a substrate having a surface;

forming at least one upstanding rod or ridge on the surface;

depositing a first layer of an electroconductor on the surface and on the at least one rod or ridge;

coating the first electroconductive layer with a layer of a dielectric; and

depositing a second layer of an electroconductor on the dielectric layer;

wherein the forming comprises:

coating the surface of the substrate with a photoresist;

patterning the photoresist to define the at least one upstanding rod or ridge therein; and

stripping the photoresist from the surface of the substrate so as to leave the at least one rod or ridge upstanding thereon.

2. The method of claim 1 , wherein the forming comprises forming an array of upstanding rods or ridges.

3. The method of claim 1 , wherein the depositing of the first layer or the depositing of the second layer comprises at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), and sputtering.

4. The method of claim 1 , wherein the coating of the first electroconductive layer with the layer of a dielectric comprises depositing a vapor phase of a polymer or forming a self-assembled monolayer (SAM).

5. The method of claim 1 , wherein the substrate includes a cavity, the surface of the substrate comprises a floor of the cavity, and the at least one upstanding rod or ridge is disposed at least partially within the cavity.

6. A capacitor, comprising:

a substrate;

an array of upstanding rods or ridges disposed on a surface of the substrate; and

a sandwich disposed over the surface of the substrate and the array of upstanding rods or ridges, the sandwich comprising at least one layer of a dielectric sandwiched between at least two electroconductive layers;

wherein at least one of the rods or ridges of the array comprises a photoresist.

7. The capacitor of claim 6 , wherein the substrate comprises at least one of a semiconductor, glass, ceramic, or a polymer.

8. The capacitor of claim 6 , wherein the photoresist comprises Benzocyclobutene (BCB), polyimide, spun-on glass, or SU-8.

9. The capacitor of claim 6 , wherein the at least one dielectric layer comprises Parylene or a self-assembled monolayer (SAM) comprising at least one thiol group.

10. The capacitor of claim 9 , wherein the SAM comprises an alkanethiol.

11. The capacitor of claim 6 , wherein the at least one dielectric layer comprises hafnium oxide (HfO 2 ), tantalum pentoxide (Ta 2 O 5 ), zirconium dioxide (ZrO 2 ), yttrium oxide (Y 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium dioxide (TiO 2 ), strontium titanate (SrTiO 3 ), or an alkanethiol having a thiol group on both ends.

12. The capacitor of claim 6 , wherein at least one of the at least two electroconductive layers comprises Tantalum (Ta), Copper (Cu), Titanium (Ti), Titanium Nitride (TiN), Silver (Ag), Gold (Au), or Palladium (Pd).

13. A capacitor, comprising:

a substrate;

an array of upstanding rods or ridges disposed on a surface of the substrate; and

a sandwich disposed over the surface of the substrate and the array of upstanding rods or ridges, the sandwich comprising at least one layer of a dielectric sandwiched between at least two electroconductive layers;

wherein the at least one dielectric layer comprises an alkanethiol having a thiol group on both ends;

wherein the alkanethiol comprises Dithiothreitol (C4H10S2), 1,2-Ethanedithiol (C2H4(SH)2), Biphenyl-4,4′-dithiol (HSC6H4SH), or 1,4-Benzenedimethanethiol (C6H4(CH2SH)2).

Assignments (4)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0668 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2017
From: WANG, LIANG; KATKAR, RAJESH; SHEN, HONG; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 042661/0445 →
Continuity (2)
Division 14304535 · Jun 13, 2014
Related Publication 20160322456A1 · Nov 3, 2016