IP Library Granted Patent US 9,741,696
Granted Patent B2
US 9,741,696 · App. 15/174,338 · Granted Aug 22, 2017

Thermal vias disposed in a substrate proximate to a well thereof

Inventors: Rajesh Katkar (San Jose, CA); Arkalgud R. Sitaram (Cupertino, CA); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: Invensas Corporation
H01L25/0657H01L21/308H01L21/30604H01L21/31105H01L21/76897H01L21/76898H01L23/3675H01L23/3677H01L23/481H01L23/5386H01L25/50H01L23/42H01L2224/16145H01L2224/16225H01L2224/32225H01L2224/73204H01L2224/73253H01L2225/06541H01L2225/06589H01L2924/15311H01L2924/16152
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Quick Facts
Patent No.
US 9,741,696
App. No.
15/174,338
Granted
Aug 22, 2017
Kind
B2
Abstract

An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

Claims (29)

1. An apparatus, comprising:

a three-dimensional stacked integrated circuit having a first die;

wherein a substrate of the first die has at least one thermal via structure extending from a first surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate;

wherein a first end of the at least one thermal via structure is proximate to the well of the substrate for conduction of heat away therefrom through the at least one thermal via structure to a second end of the at least one thermal via structure;

wherein the substrate includes a semiconductor-on-insulator substrate having a buried dielectric layer; and

wherein the first end stops on the buried dielectric layer of the substrate.

2. The apparatus according to claim 1 , further comprising:

a pad associated with a second surface of the substrate opposite the first surface of the substrate;

wherein the at least one thermal via structure is a plurality of thermal via structures;

wherein widths of the plurality of thermal via structures are each less than widths of through substrate via structures of the substrate; and

wherein the pad is an etch stop layer for the through substrate via structures.

3. The apparatus according to claim 2 , wherein the widths of the plurality of thermal via structures are in a range of approximately 0.5 to 100 microns.

4. The apparatus according to claim 3 , wherein:

the plurality of thermal via structures are in a high-density array with a pitch in a range of approximately 1 to 200 microns; and

the width of the at least one through substrate via structure is in a range of approximately 1 to 5 times any of the widths of the plurality of thermal via structures.

5. The apparatus according to claim 1 , wherein depth of the at least one thermal via structure is approximately 1 to 200 microns which is approximately 1 to 20 microns less than a depth of the at least one through substrate via structure.

6. The apparatus according to claim 1 , wherein the at least one through substrate via structure is a signal via structure.

7. The apparatus according to claim 1 , wherein the at least one through substrate via structure is a thermal via structure.

8. The apparatus according to claim 1 , wherein the first end is within 20 microns inclusive of the well.

9. The apparatus according to claim 1 , wherein the buried dielectric layer is of a partial silicon-on-insulator wafer.

10. The apparatus according to claim 1 , wherein the at least one through substrate via structure extends through the buried dielectric layer.

11. The apparatus according to claim 10 , wherein the at least one through substrate via structure extends through a gap between dielectric islands of the buried dielectric layer.

12. The apparatus according to claim 1 , further comprising:

a pad associated with a second surface of the substrate opposite the first surface of the substrate;

wherein the at least one thermal via structure is a plurality of thermal via structures;

the plurality of thermal via structures extending from the first surface of the substrate toward the well of the substrate without extending to the well and without extending through the substrate;

first ends of the plurality of thermal via structures are proximate to the well of the substrate for conduction of heat away therefrom through the plurality of thermal via structures to corresponding second ends of the plurality of thermal via structures; and

the second ends of the plurality of thermal via structures are coupled to a heat sink.

13. The apparatus according to claim 12 , wherein an air gap is located between sidewalls of the plurality of thermal via structures and the substrate to provide fins.

Assignments (7)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0668 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2016
From: KATKAR, RAJESH; SITARAM, ARKALGUD R.; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 039007/0275 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2016
From: KATKAR, RAJESH; SITARAM, ARKALGUD R.; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 038819/0701 →
Continuity (2)
Continuation 14201585 · Mar 7, 2014
Related Publication 20160284672A1 · Sep 29, 2016