IP Library Granted Patent US 10,381,326
Granted Patent B2
US 10,381,326 · App. 14/289,483 · Granted Aug 13, 2019

Structure and method for integrated circuits packaging with increased density

Inventors: Charles G. Woychik (San Jose, CA); Arkalgud R. Sitaram (Cupertino, CA); Andrew Cao (Fremont, CA); Bong-Sub Lee (Mountain View, CA)
Assignee: Invensas Corporation
H01L25/0657H01L21/56H01L21/561H01L21/6835H01L21/76898H01L23/29H01L23/3107H01L23/3128H01L23/367H01L23/3731H01L23/481H01L24/02H01L24/13H01L24/14H01L24/17H01L24/92H01L24/94H01L24/97H01L25/03H01L25/0652H01L25/18H01L25/50H01L21/563H01L23/295H01L24/81H01L2221/68327H01L2221/68331H01L2224/0231H01L2224/02372H01L2224/0401H01L2224/05568H01L2224/05573H01L2224/05611H01L2224/05647H01L2224/05655H01L2224/05664H01L2224/131H01L2224/13022H01L2224/13109H01L2224/13111H01L2224/13124H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/13164H01L2224/13193H01L2224/14155H01L2224/14181H01L2224/16145H01L2224/16146H01L2224/16235H01L2224/1703H01L2224/17051H01L2224/17181H01L2224/2919H01L2224/2929H01L2224/29388H01L2224/32145H01L2224/32225H01L2224/73104H01L2224/73204H01L2224/92125H01L2224/94H01L2224/97H01L2225/06513H01L2225/06541H01L2225/06568H01L2225/06589H01L2924/15311H01L2924/18161
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Quick Facts
Patent No.
US 10,381,326
App. No.
14/289,483
Granted
Aug 13, 2019
Kind
B2
Abstract

A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.

Claims (17)

1. An assembly comprising:

a first module comprising a plurality of microelectronic elements separated by an interposer; and

a second module comprising:

a first microelectronic element attached to a top side of the first module;

one or more wire bond wires each of which is attached to a bottom side of the first microelectronic element of the second module and extends beyond a top of the first module, the one or more wire bond wires for electrical conduction or thermal conduction; and

a third module comprising a second microelectronic element underlying the first module and attached to each of the one or more wire bond wires, the first module lying between the first microelectronic element of the second module and the second microelectronic element of the third module.

2. The assembly of claim 1 , wherein the first module is attached to the second microelectronic element of the third module.

3. The assembly of claim 1 , wherein the one or more wire bond wires are first one or more wire bond wires; and wherein the third module further comprises one or more second wire bond wires each having a first end attached to the second microelectronic element of the third module and each having a second end extending upward beyond the first module and a bottom surface of the first microelectronic element of the second module.

4. An assembly comprising a plurality of modules, each module of the plurality of modules of the assembly comprising:

an interposer comprising one or more first vias extending through a substrate of the interposer from a first side of the substrate to a second side of the substrate;

a first microelectronic element having first contacts coupled to the first side of the substrate for electrical conductivity to at least one of the one or more first vias;

a second microelectronic element coupled to the second side of the substrate through second contacts, the second contacts coupled to an upper surface of the second microelectronic element for electrical conductivity between at least one of the one or more first vias and at least one or more second vias of the second microelectronic element; and

one or more wire bond wires each having a first end coupled to the upper surface of the second microelectronic element and having a second end opposite the first end corresponding thereto extending past an upper surface of the first microelectronic element, the one or more wire bond wires for electrical conduction or thermal;

wherein the plurality of modules include a first module and a second module, wherein the second microelectronic element of the second module is attached to the second microelectronic element of the first module.

5. The assembly of claim 4 , wherein each of the plurality of modules further comprises:

a third microelectronic element attached to the second end of at least one of the one or more wire bond wires associated with the first microelectronic element; and

a forth microelectronic element attached to the second end of at least one of the one or more wire bond wires associated with the second microelectronic element.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0668 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2015
From: WOYCHIK, CHARLES G.; SITARAM, ARKALGUD R.; CAO, ANDREW; LEE, BONG-SUB
To: INVENSAS CORPORATION
Reel/Frame 035268/0944 →
Continuity (1)
Related Publication 20150348940A1 · Dec 3, 2015
Cited By (4)
US 12,237,290 US 12,424,574 US 12,444,691 US 12,713,924