Semiconductor packages and methods of manufacturing the semiconductor packages
A semiconductor package includes a first semiconductor chip including a first substrate having first and second surfaces opposite to each other, a through electrode in the first substrate, a first chip pad on the first surface and electrically connected to the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first substrate; a redistribution wiring layer on the first surface of the first semiconductor chip, and including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad; a second semiconductor chip stacked on the second surface of the first semiconductor chip and electrically connected to the through electrode; and a molding member on side surfaces of the first and second semiconductor chips.
1. A semiconductor package comprising:
a first semiconductor chip including a first semiconductor substrate having a first surface and a second surface opposite to the first surface, a through electrode that extends through the first semiconductor substrate, a first chip pad on the first surface and electrically connected to a first end of the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first semiconductor substrate;
a redistribution wiring layer on and integrally with the first surface of the first semiconductor chip such that there is no space between the first surface of the first semiconductor substrate and the redistribution wiring layer, the redistribution wiring layer including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad;
an insulation layer on the second surface of the first semiconductor substrate, the insulation layer having an upper surface that is planar across the second surface of the first semiconductor substrate;
a planar third chip pad in the insulation layer on the second surface of the first semiconductor substrate and electrically connected to a second end of the through electrode opposite the first end of the through electrode, the third chip pad having an upper surface that is exposed from the upper surface of the insulation layer, the upper surface of the third chip pad being coplanar with the upper surface of the insulation layer;
a second semiconductor chip stacked on the second surface of the first semiconductor chip, overlapping the first, second and third chip pads and the through electrode in a vertical direction, the second semiconductor chip electrically connected to the through electrode via the third chip pad and electrically isolated from the second redistribution wiring line;
an adhesive layer on an outer surface of the second semiconductor chip; and
a molding member on a side surface of the first semiconductor chip, a side surface of the redistribution wiring layer, a side surface of the second semiconductor chip, a side surface of the insulation layer and a side surface of the adhesive layer,
wherein the side surface of the redistribution wiring layer is coplanar with the side surface of the first semiconductor chip and the side surface of the second semiconductor chip.
2. The semiconductor package of claim 1 , wherein the molding member extends between the first semiconductor chip and the second semiconductor chip.
3. The semiconductor package of claim 1 , further comprising:
a second adhesive layer between the first semiconductor chip and the second semiconductor chip to adhere the first and second semiconductor chips to each other.
4. The semiconductor package of claim 1 , further comprising:
a conductive bump interposed between the first semiconductor chip and the second semiconductor chip to electrically connect the through electrode to the second semiconductor chip,
wherein no conductive bump between the first semiconductor chip and the second semiconductor chip is electrically connected to the second redistribution wiring line.
5. The semiconductor package of claim 4 , wherein the conductive bump has a diameter of about 10 micrometers (μm) to about 100 (μm).
6. The semiconductor package of claim 4 , wherein the second semiconductor chip includes a second semiconductor substrate and a fourth chip pad on a third surface of the second semiconductor substrate that faces the second surface of the first semiconductor substrate, wherein the conductive bump is on the fourth chip pad, and wherein the fourth chip pad and the conductive bump are between the first and second semiconductor substrates, the semiconductor package further comprising an insulation interlayer on the third surface of the second semiconductor substrate, the fourth chip pad being in an outermost insulation layer of the insulation interlayer.
7. The semiconductor package of claim 1 , further comprising:
outer connection members on an outer surface of the redistribution wiring layer.
8. The semiconductor package of claim 7 , wherein the outer connection members include a first solder ball electrically connected to the first redistribution wiring line and a second solder ball electrically connected to the second redistribution wiring line.
9. The semiconductor package of claim 8 , wherein the first and second solder balls each have a diameter of about 300 micrometers (μm) to about 500 μm.
10. The semiconductor package of claim 1 , wherein the first semiconductor chip further includes an insulation interlayer on the first surface of the first semiconductor chip, wherein the insulation interlayer has the first and second chip pads in an outer surface thereof.
11. The semiconductor package of claim 1 , wherein the second semiconductor chip is connected to the first semiconductor chip without bond wires.
12. A semiconductor package comprising:
a first semiconductor chip including a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and including a first chip pad in the first surface electrically connected to a first end of a through electrode that extends through the first semiconductor substrate of the first semiconductor chip and a second chip pad in the first surface electrically connected to a circuit element that is in the first semiconductor substrate;
an insulation layer on the second surface of the first semiconductor substrate, the insulation layer having an upper surface that is planar across the second surface of the first semiconductor substrate;
a planar third chip pad in the insulation layer on the second surface of the first semiconductor substrate and electrically connected to a second end of the through electrode opposite the first end of the through electrode, the third chip pad having an upper surface that is exposed from an upper surface of the insulation layer, the upper surface of the third chip pad being coplanar with the upper surface of the insulation layer;
a second semiconductor chip stacked on the second surface of the first semiconductor substrate, extending across the first, second and third chip pads and the through electrode in a vertical direction, the second semiconductor chip electrically connected to the through electrode of the first semiconductor chip by a conductive bump between the third chip pad and the second semiconductor chip;
a redistribution wiring layer on and integrally with the first surface of the first semiconductor substrate such that there is a continuous interface between the first surface of the first semiconductor substrate and the redistribution wiring layer, the redistribution wiring layer including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad;
an adhesive layer on an outer surface of the second semiconductor chip; and
a molding member on a side surface of the first semiconductor chip, a side surface of the redistribution wiring layer, a side surface of the second semiconductor chip, a side surface of the insulation layer and a side surface of the adhesive layer,
wherein the side surface of the redistribution wiring layer is coplanar with the side surface of the first semiconductor chip and the side surface of the second semiconductor chip,
wherein the first redistribution wiring line and the through electrode collectively provide a first input/output signal line for the second semiconductor chip, and
wherein the second redistribution wiring line provides a second input/output signal line for the first semiconductor chip and not for the second semiconductor chip; and
outer connection members on an outer surface of the redistribution wiring layer and electrically connected to the first and second redistribution wiring lines, respectively.
13. The semiconductor package of claim 12 , wherein the molding member extends between the first semiconductor chip and the second semiconductor chip.
14. The semiconductor package of claim 12 , further comprising:
a second adhesive layer between the first semiconductor chip and the second semiconductor chip to adhere the first and second semiconductor chips to each other.
15. The semiconductor package of claim 12 , wherein the molding member is on the outer surface of the redistribution wiring layer.
16. The semiconductor package of claim 12 , wherein the conductive bump has a diameter of about 10 micrometers (μm) to about 100 μm.
17. The semiconductor package of claim 12 , wherein the outer connection members include a first solder ball electrically connected to the first redistribution wiring line and a second solder ball electrically connected to the second redistribution wiring line.
18. The semiconductor package of claim 12 ,
wherein the first and second input/output signal lines are electrically isolated from each other, and
wherein no through electrode of the first semiconductor chip is part of the second input/output signal line.
19. The semiconductor package of claim 12 ,
wherein the second semiconductor chip includes a second semiconductor substrate and a fourth chip pad in a third surface of the second semiconductor substrate that faces the second surface of the first semiconductor substrate, wherein the fourth chip pad is between the first semiconductor substrate and the second semiconductor substrate,
wherein the conductive bump comprises a first conductive bump that is between the third and fourth chip pads,
wherein the through electrode comprises a first through electrode, and
wherein the semiconductor package further comprises a second through electrode that extends through the first semiconductor substrate and a second conductive bump that electrically connects the second semiconductor chip to the second through electrode.
20. A fan-in, wafer level semiconductor package comprising:
a redistribution wiring layer including a first redistribution wiring line and a second redistribution wiring line on a first surface of the redistribution wiring layer;
a first semiconductor chip on and integrally with the redistribution wiring layer such that there is a continuous interface between the first surface of the redistribution wiring layer and the first semiconductor chip, the first semiconductor chip including a first semiconductor substrate, a first chip pad electrically connected to the first redistribution wiring line, a second chip pad electrically connected to the second redistribution wiring line, and a through electrode electrically connected to the first chip pad, wherein the through electrode extends through the first semiconductor substrate, wherein the first and second chip pads are on a first surface of the first semiconductor substrate, wherein there is an absence of solder bumps between the first and second chip pads and the redistribution wiring layer, and wherein no through electrode of the first semiconductor chip is electrically connected to the second chip pad;
an insulation layer on a second surface of the first semiconductor substrate, the insulation layer having an upper surface that is planar across the second surface of the first semiconductor substrate;
a planar third chip pad in the insulation layer on a second surface of the first semiconductor substrate opposite the first surface of the first semiconductor substrate and electrically connected to the through electrode, the third chip pad having an upper surface that is exposed from an upper surface of the insulation layer, the upper surface of the third chip pad being coplanar with the upper surface of the insulation layer;
a second semiconductor chip stacked on the first semiconductor chip, extending across the first, second and third chip pads and the through electrode, the second semiconductor chip electrically connected to the through electrode via the third chip pad;
an adhesive layer on an outer surface of the second semiconductor chip;
a molding member that continuously extends along each of a side surface of the first semiconductor chip, a side surface of the redistribution wiring layer, a side surface of the second semiconductor chip, a side surface of the insulation layer and a side surface of the adhesive layer; and
outer connection members on a second surface of the redistribution wiring layer opposite the first surface,
wherein the side surface of the redistribution wiring layer is coplanar with the side surface of the first semiconductor chip and the side surface of the second semiconductor chip.