IP Library Granted Patent US 9,818,668
Granted Patent B2
US 9,818,668 · App. 15/066,983 · Granted Nov 14, 2017

Thermal vias disposed in a substrate without a liner layer

Inventor: Guilian Gao (San Jose, CA)
Assignee: Invensas Corporation
H01L23/3677H01L21/308H01L21/30604H01L21/30625H01L21/31111H01L21/3212H01L21/486H01L21/4882H01L21/76829H01L21/76843H01L21/76898H01L23/481H01L23/538H01L2224/16145H01L2224/16225H01L2224/32225H01L2224/73204H01L2224/73253H01L2924/15311H01L2924/16152
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Quick Facts
Patent No.
US 9,818,668
App. No.
15/066,983
Granted
Nov 14, 2017
Kind
B2
Abstract

A method relating generally to a substrate is disclosed. In such a method, the substrate has formed therein a plurality of vias. A liner layer is located on the substrate, including being located in a subset of the plurality of vias. At least one of the plurality of vias does not have the liner layer located therein. A thermally conductive material is disposed in the at least one of the plurality of vias to provide a thermal via structure.

Claims (57)

1. A method, comprising:

patterning a first masking layer deposited on an upper surface of a substrate to define a plurality of openings;

etching the substrate through the plurality of openings to form corresponding via openings in the substrate;

wherein each of the via openings include at least a sidewall surface and a base surface;

removing the first masking layer;

depositing a liner layer on the upper surface of the substrate and in the via openings on the sidewall surface and the base surface of each thereof;

patterning a second masking layer deposited on the liner layer to define at least one opening corresponding to at least one of the via openings;

wherein the at least one opening exposes a portion of the liner layer corresponding to the at least one of the via openings;

etching the portion of the liner layer to expose the sidewall surface and the base surface of the at least one of the via openings;

removing the second masking layer;

depositing a barrier layer on the liner layer and on the sidewall surface and the base surface of the at least one of the via openings;

depositing a thermally conductive material on the barrier layer;

wherein the thermally conductive material is deposited in the via openings to provide signal via structures and at least one thermal via structure; and

wherein the depositing of the thermally conductive material comprises depositing different thermally conductive materials for the signal via structures as compared with the at least one thermal via structure.

2. The method according to claim 1 , further comprising polishing the thermally conductive material, the barrier layer, and the liner layer down to the upper surface of the substrate.

3. The method according to claim 1 , further comprising polishing the thermally conductive material and the barrier layer down to an upper surface of the liner layer.

4. The method according to claim 1 , further comprising polishing a lower surface of the substrate and the barrier layer for removal therefrom to temporarily expose a lower surface of the thermally conductive material in the at least one of the via openings to provide a corresponding at least one through substrate thermal via as the at least one thermal via structure.

5. The method according to claim 1 , further comprising polishing a lower surface of the substrate, the barrier layer, and the liner layer for removal therefrom to temporarily expose a lower surface of the thermally conductive material in the via openings to provide the signal via structures and the at least one thermal via structure.

6. The method according to claim 1 , wherein the thermally conductive material has a thermal conductivity value equal to or greater than approximately 150 W/(mK).

7. The method according to claim 6 , wherein:

the barrier layer has a thermal conductivity value in a range of approximately 5 to 70 W/(mK); and

the liner layer has a thermal conductivity value equal to or less than approximately 3 W/(mK).

8. A method for forming an integrated circuit, comprising:

forming openings in a substrate;

forming a liner layer on sidewall and base surfaces in a first set of the openings;

depositing a barrier layer on the liner layer in the first set of the openings and on sidewall and base surfaces in a second set of the openings;

depositing a thermally conductive material on the barrier layer in the second set of the openings to provide a thermal via structure;

depositing an electrically conductive material on the barrier layer in the first set of the openings to provide a signal via structure; and

wherein the thermally conductive material and the electrically conductive material are different materials with respect to one another.

9. The method according to claim 8 , wherein the depositing of the thermally conductive material comprises:

masking the first set of the openings; and

unmasking the first set of the openings after the depositing of the thermally conductive material.

10. The method according to claim 8 , wherein the depositing of the electrically conductive material comprises:

masking the second set of the openings; and

unmasking the second set of the openings after the depositing of the electrically conductive material.

11. The method according to claim 8 , wherein the forming of the liner layer comprises:

depositing the liner layer on the sidewall and base surfaces of the first and the second set of the openings;

masking the first set of the openings;

removing the liner layer from the second set of the openings; and

unmasking the first set of the openings.

12. The method according to claim 8 , wherein the thermal via structure is not electrically conductive in comparison to the signal via structure.

13. The method according to claim 8 , wherein the thermally conductive material has a thermal conductivity value equal to or greater than approximately 150 W/(mK).

14. The method according to claim 8 , wherein the barrier layer has a thermal conductivity value in a range of approximately 5 to 70 W/(mK).

15. The method according to claim 8 , wherein the liner layer has a thermal conductivity value equal to or less than approximately 3 W/(mK).

16. A method for forming an integrated circuit, comprising:

forming openings in a substrate;

forming a liner layer on sidewall and base surfaces in a first set of the openings;

depositing a barrier layer on the liner layer in the first set of the openings;

depositing a thermally conductive material on sidewall and base surfaces in a second set of the openings to provide a thermal via structure;

depositing an electrically conductive material on the barrier layer in the first set of the openings to provide a signal via structure; and

wherein the thermally conductive material and the electrically conductive material are different materials with respect to one another.

17. The method according to claim 16 , wherein:

the thermally conductive material is not a diffusion or migration risk with respect to contamination of the substrate; and

the thermal via structure is not electrically conductive in comparison to the signal via structure.

18. The method according to claim 16 , wherein the thermally conductive material has a thermal conductivity value equal to or greater than approximately 150 W/(mK).

19. The method according to claim 18 , wherein the barrier layer has a thermal conductivity value in a range of approximately 5 to 70 W/(mK).

20. The method according to claim 19 , wherein the liner layer has a thermal conductivity value equal to or less than approximately 3 W/(mK).

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0668 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2016
From: GAO, GUILIAN
To: INVENSAS CORPORATION
Reel/Frame 037950/0532 →
Continuity (2)
Division 14201473 · Mar 7, 2014
Related Publication 20160197026A1 · Jul 7, 2016