Tall and fine pitch interconnects

1. A method, comprising:

applying a conductive layer to a carrier;

forming patterned interconnect structures comprising reflowable conductive material on a surface of the conductive layer;

etching the conductive layer to remove portions of the conductive layer to form a patterned conductive structure, such that at least portions of the conductive layer covered by the patterned interconnect structures are not removed;

mounting a first microelectronic element to the patterned interconnect structures;

removing the carrier; and

mounting a second microelectronic element with interconnect structures onto the patterned conductive structure, on a side previously occupied by the carrier.

2. The method of claim 1 , further comprising coupling the conductive layer to the carrier using a temporary adhesive.

3. The method of claim 1 , further comprising screen printing the reflowable conductive material onto the conductive layer to form the patterned interconnect structures.

4. The method of claim 1 , further comprising etching the conductive layer and the reflowable conductive material during a same process to form the patterned interconnect structures and the patterned conductive structure concurrently.

5. The method of claim 1 , further comprising coupling the first microelectronic element to the patterned interconnect structures via heated reflow.

6. The method of claim 1 , further comprising coupling the second microelectronic element to the patterned conductive structure via heated reflow, wherein the interconnect structures of the second microelectronic element are comprised of reflowable conductive material.

7. The method of claim 1 , wherein the conductive layer comprises a metallic foil.

8. The method of claim 1 , wherein the conductive layer comprises one or more deposited conductive layers.

9. The method of claim 1 , wherein the interconnect structures of the second microelectronic element comprise solder bumps.

10. The method of claim 1 , wherein the reflowable conductive material comprises a solder or a solder-composite material.

11. A method, comprising:

providing a first microelectronic element having a first reflowable material component formed on a surface of the first microelectronic element, and having a non-reflowable material component formed on the first reflowable material component away from the surface of the first microelectronic element;

providing a second microelectronic element having a second reflowable material component formed on a surface of the second microelectronic element; and

electrically coupling the first microelectronic element to the second microelectronic element by coupling the second reflowable material component to the non-reflowable material component,

wherein the non-reflowable material component includes a patterned layer that is nonwettable with respect to a material of at least one of the first and the second reflowable material components.

12. The method of claim 11 , further comprising coupling the second reflowable material component to the non-reflowable material component via a heated reflow process.

13. The method of claim 11 , wherein at least one of the first and second microelectronic elements is taken from the group comprising: an integrated chip (IC) die, a printed circuit board (PCB), a semiconductor wafer, a semiconductor package, a silicon-based carrier, a glass carrier, and a ceramic carrier.

14. The method of claim 11 , wherein at least one of the first and second reflowable material components comprises a solder or a solder-composite material and the non-reflowable material component comprises a metallic structure.

15. A method, comprising:

applying a nonwettable layer to at least a first side of a conductive layer;

patterning the nonwettable layer to form nonwettable barriers with open interiors on at least the first side of the conductive layer;

depositing a reflowable conductive material on the conductive layer within the open interiors of the nonwettable barriers to form interconnect structures;

mounting a first microelectronic element to the interconnect structures;

mounting an integrated circuit (IC) die with interconnect structures onto the conductive structure, such that the interconnect structures of the second microelectronic element are located within the open interiors of the nonwettable barriers; and

underfilling between the second microelectronic element and the first microelectronic element.

16. The method of claim 15 , further comprising patterning the conductive layer to form conductive pads covering the open interiors of the nonwettable barriers; and depositing the reflowable conductive material onto the conductive pads within the open interiors of the nonwettable barriers to form the interconnect structures.

17. The method of claim 16 , further comprising patterning the conductive layer to form conductive traces electrically coupling two or more of the conductive pads.

18. The method of claim 16 , wherein a combination of the nonwettable barriers and the conductive layer holds the conductive pads in a desired physical arrangement during processing, including during depositing the reflowable conductive material, mounting the first microelectronic element, and/or mounting the second microelectronic element.

19. The method of claim 15 , wherein the nonwettable barriers have a closed or partly-closed ring-like shape with an open interior.

20. A method, comprising:

depositing patterned reflowable conductive material on a first microelectronic element;

applying a resist layer to the first microelectronic element, between the patterned reflowable conductive material;

depositing a conductive layer onto the resist layer and the patterned reflowable conductive material;

depositing a nonwettable layer over the conductive layer;

patterning the nonwettable layer to form nonwettable barriers on the conductive layer;

applying a mask to at least portions of the nonwettable barriers and the conductive layer;

etching the conductive layer to form conductive structures;

removing the mask and the resist layer;

reflowing the reflowable conductive material to the first microelectronic element;

mounting a second microelectronic element with interconnect structures onto the conductive structures, such that the interconnect structures of the second microelectronic element are located between the nonwettable barriers; and

underfilling between the second microelectronic element and the first microelectronic element.

21. The method of claim 20 , further comprising depositing a diffusion barrier layer and/or a precious metal layer to one or more sides of the conductive layer.

22. A method, comprising:

depositing a non-reflowable conductive material over a first reflowable conductive material component to form a first portion of an interconnect structure;

coupling a second reflowable conductive material component to the non-reflowable conductive material, on a side opposite the first reflowable conductive material component, to form the interconnect structure,

wherein the non-reflowable conductive material includes a patterned layer that is nonwettable with respect to a material of at least one of the first and the second reflowable conductive material components.

23. The method of claim 22 , further comprising coupling the second reflowable conductive material to the non-reflowable conductive material via heated reflow.