IP Library Granted Patent US 10,446,456
Granted Patent B2
US 10,446,456 · App. 15/865,842 · Granted Oct 15, 2019

Integrated circuits protected by substrates with cavities, and methods of manufacture

Inventors: Hong Shen (Oak Park, CA); Charles G. Woychik (San Jose, CA); Arkalgud R. Sitaram (Cupertino, CA)
Assignee: Invensas Corporation
H01L23/055H01L21/2885H01L21/4803H01L21/486H01L21/56H01L21/76879H01L21/76897H01L23/04H01L23/147H01L23/315H01L23/3107H01L23/3675H01L23/481H01L23/49827H01L23/49838H01L23/5389H01L24/97H01L25/0652H01L25/0655H01L25/50H01L21/561H01L23/10H01L23/49816H01L2224/16145H01L2224/16225H01L2224/32225H01L2224/73204H01L2225/06548H01L2225/06555H01L2924/12042H01L2924/15311H01L2924/181
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Quick Facts
Patent No.
US 10,446,456
App. No.
15/865,842
Filed
Jan 9, 2018
Granted
Oct 15, 2019
Kind
B2
Art Unit
2818
USPC
257/690
Abstract

Dies ( 110 ) with integrated circuits are attached to a wiring substrate ( 120 ), possibly an interposer, and are protected by a protective substrate ( 410 ) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Claims (19)

1. A structure comprising:

(a) an assembly comprising:

a first substrate comprising one or more first contact pads at a top side of the first substrate;

one or more modules attached to, and forming an upward protrusion over, the first substrate, each module comprising one or more semiconductor integrated circuits and one or more contact pads coupled to one or more circuits in the one or more semiconductor integrated circuits, each contact pad being attached to a respective first contact pad;

(b) a first layer on a top side of the assembly, the first layer overlying the one or more modules, the first layer having a top surface having a protrusion over each module; and

(c) a second substrate comprising one or more cavities;

wherein the first layer is bonded to the second substrate, each said protrusion of the top surface of the first layer being bonded to a surface of a corresponding cavity in the second substrate, and at least part of each semiconductor integrated circuit is located in a corresponding cavity in the second substrate;

wherein the second substrate comprises:

a constituent substrate of a selected material, the one or more cavities extending into the constituent substrate; and

a second layer of a material different from the selected material, the second layer extending into the one or more cavities;

wherein the first layer is directly bonded to the second layer; and

wherein the first layer is bonded to the second layer in an area outside the one or more cavities.

2. The structure of claim 1 wherein part of a top surface of the first layer is spaced from the second layer.

3. The structure of claim 1 wherein the first layer is bonded to the second layer around each said cavity.

4. The structure of claim 1 wherein the second layer covers each module.

5. The structure of claim 1 wherein, for each module, the second layer covers the module and an area adjacent to the module and laterally surrounding the module.

6. The structure of claim 1 wherein the second layer covers the assembly.

7. The structure of claim 6 wherein an entire bottom surface of the second layer is the same material.

8. The structure of claim 1 wherein bonding of the first layer to the second layer improves a thermal conductivity of a thermal path between at least one of the one or more modules and the second substrate.

Assignments (4)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0668 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2018
From: SHEN, HONG; WOYCHIK, CHARLES G.; SITARAM, ARKALGUD R.
To: INVENSAS CORPORATION
Reel/Frame 044575/0339 →
Continuity (4)
Division 15265148 · Sep 14, 2016
Continuation 14214365 · Mar 14, 2014
Provisional Application 61952066 · Mar 12, 2014
Related Publication 20180130717A1 · May 10, 2018
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