IP Library Granted Patent US 9,397,038
Granted Patent B1
US 9,397,038 · App. 14/633,746 · Granted Jul 19, 2016

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

Inventors: Cyprian Emeka Uzoh (San Jose, CA); Charles G. Woychik (San Jose, CA); Arkalgud R. Sitaram (Cupertino, CA); Hong Shen (Palo Alto, CA); Zhuowen Sun (Campbell, CA); Liang Wang (Milpitas, CA); Guilian Gao (San Jose, CA)
Assignee: Invensas Corporation
H01L23/5223H01L21/76802H01L21/76877H01L23/5226H01L28/60
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Quick Facts
Patent No.
US 9,397,038
App. No.
14/633,746
Granted
Jul 19, 2016
Kind
B1
Abstract

In a microelectronic component having conductive vias ( 114 ) passing through a substrate ( 104 ) and protruding above the substrate, conductive features ( 120 E.A, 120 E.B) are provided above the substrate that wrap around the conductive vias' protrusions ( 114 ′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Claims (66)

1. A microelectronic component comprising:

a substrate comprising a top surface, a bottom surface, and one or more first through-holes, each first through-hole passing between the top surface and the bottom surface;

one or more conductive vias protruding from the one or more first through-holes to form at each first through-hole a conductive protrusion above the substrate;

for each conductive protrusion protruding from a corresponding first through-hole, a first conductive sleeve region wrapping around the conductive protrusion and extending at least along a segment of the conductive protrusion, the first conductive sleeve region being electrically insulated from any conductive protrusion protruding from the first through-hole above the substrate, the first conductive sleeve region comprising an inner surface facing the conductive protrusion, an outer surface opposite to the inner surface, and a thickness which is a distance between the inner and outer surfaces, a maximum value of the thickness being smaller than a length of the inner surface measured along the segment.

2. The microelectronic component of claim 1 wherein for each conductive protrusion, the first conductive sleeve region is laterally spaced from the first through-hole towards outside of the first through-hole.

3. The microelectronic component of claim 1 wherein the substrate further comprises one or more second through-holes each of which passes between the top surface and the bottom surface; and

the microelectronic component further comprises:

one or more conductive vias protruding from the one or more second through-holes to form at each second through-hole a conductive protrusion above the substrate;

for each conductive protrusion protruding from a corresponding second through-hole, a conductive feature electrically interconnecting the conductive protrusion and at least one first conductive sleeve region.

4. The microelectronic component of claim 1 wherein the substrate comprises a cavity in the top surface, each conductive protrusion is at least partially located in the cavity;

the substrate further comprises one or more second through-holes, each second through-hole passing between the top surface and the bottom surface outside the cavity; and

the microelectronic component further comprises one or more conductive vias each of which passes through a corresponding second through-hole and is electrically coupled to a circuit element above the substrate and a circuit element below the substrate.

5. The microelectronic component of claim 1 further comprising, for each conductive protrusion, a corresponding second conductive sleeve region extending at least along said segment of the conductive protrusion and wrapping around the first conductive sleeve region, the second conductive sleeve region being separated from the first conductive sleeve region by a dielectric film.

6. The microelectronic component of claim 1 comprising a conductive layer comprising each first conductive sleeve region;

wherein the conductive layer covers the top surface of the substrate except for any area underlying any area surrounded by any first conductive sleeve region.

7. The microelectronic component of claim 1 wherein each conductive via passes through the corresponding first through-hole and provides a conductive path between a circuit element below the substrate and a circuit element above the substrate.

8. A microelectronic component comprising:

a substrate comprising a top surface, a bottom surface, and one or more first through-holes, each first through-hole passing between the top surface and the bottom surface;

one or more first conductive vias protruding from the one or more first through-holes to form at each first through-hole a conductive protrusion above the substrate;

for each conductive protrusion protruding from a corresponding first through-hole the microelectronic component comprises:

a first conductive sleeve region wrapping around the conductive protrusion and extending at least along a segment of the conductive protrusion, the first conductive sleeve region being electrically insulated from any conductive protrusion protruding from the first through-hole above the substrate; and

a second conductive sleeve region extending at least along said segment of the conductive protrusion and wrapping around the first conductive sleeve region, the second conductive sleeve region being separated from the first conductive sleeve region by a dielectric film.

9. The microelectronic component of claim 8 wherein for each conductive protrusion, the first conductive sleeve region is laterally spaced from the first through-hole towards outside of the first through-hole.

10. The microelectronic component of claim 8 wherein the substrate further comprises one or more second through-holes, each second through-hole passing between the top surface and the bottom surface; and

the microelectronic component further comprises:

one or more conductive vias protruding from the one or more second through-holes to form at each second through-hole a conductive protrusion above the substrate;

for each conductive protrusion protruding from a corresponding second through-hole, a conductive feature electrically interconnecting the conductive protrusion and at least one first conductive sleeve region or at least one second conductive sleeve region.

11. The microelectronic component of claim 8 wherein the substrate comprises a cavity in the top surface, each conductive protrusion is at least partially located in the cavity;

the substrate further comprises one or more second through-holes, each second through-hole passing between the top surface and the bottom surface outside the cavity; and

the microelectronic component further comprises one or more second conductive vias, each second conductive via passing through a corresponding second through-hole and is electrically coupled to a circuit element above the substrate and a circuit element below the substrate.

12. The microelectronic component of claim 8 comprising:

a first conductive layer comprising each first conductive sleeve region;

a second conductive layer comprising each second conductive sleeve region and electrically insulated from the first conductive layer;

a dielectric film insulating the first conductive layer from the second conductive layer;

wherein the first conductive layer covers the top surface of the substrate except for any area underlying any area surrounded by any first conductive sleeve region; and

wherein the second conductive layer covers the top surface of the substrate except for any area underlying any area surrounded by any second conductive sleeve region.

13. The microelectronic component of claim 8 comprising a capacitor having a first electrode and a second electrode which comprise, respectively, at least one first conductive sleeve region and the corresponding second conductive sleeve region, the first and second electrodes being accessible for electrical contact from another component.

14. The microelectronic component of claim 8 wherein each first conductive via passes through the corresponding first through-hole and provides a conductive path between a circuit element below the substrate and a circuit element above the substrate.

15. A manufacturing method comprising:

providing a structure comprising:

a substrate comprising a top surface, a bottom surface, and one or more first through-holes each of which passes between the top surface and the bottom surface;

one or more conductive vias protruding from the one or more first through-holes to form at each first through-hole a conductive protrusion above the substrate;

after providing the structure, forming over the substrate, for each conductive protrusion protruding from a corresponding first through-hole, a first conductive sleeve region wrapping around the conductive protrusion and extending at least along a segment of the conductive protrusion, the first conductive sleeve region being electrically insulated from any conductive protrusion protruding from the first through-hole above the substrate, the first conductive sleeve region comprising an inner surface facing the conductive protrusion, an outer surface opposite to the inner surface, and a thickness which is a distance between the inner and outer surfaces, a maximum value of the thickness being smaller than a length of the inner surface measured along the segment.

16. The method of claim 15 wherein for each conductive protrusion, the first conductive sleeve region is laterally spaced from the first through-hole towards outside of the first through-hole.

17. The method of claim 15 wherein the substrate further comprises one or more second through-holes each second through-hole passing between the top surface and the bottom surface; and

the structure further comprises one or more conductive vias protruding from the one or more second through-holes to form at each second through-hole a conductive protrusion above the substrate; and

the method further comprises, after providing the structure, forming over the substrate, for each conductive protrusion protruding from a corresponding second through-hole, a conductive feature electrically interconnecting the conductive protrusion and at least one first conductive sleeve region.

18. The method of claim 15 further comprising, after providing the structure, forming over the substrate, for each conductive protrusion, a corresponding second conductive sleeve region extending at least along said segment of the conductive protrusion and wrapping around the first conductive sleeve region, the second conductive sleeve region being separated from the first conductive sleeve region by a dielectric film.

19. The method of claim 18 wherein:

forming each first conductive sleeve region comprises forming a first conductive layer comprising each first conductive sleeve region;

forming each second conductive sleeve region comprises forming a second conductive layer comprising each second conductive sleeve region and electrically insulated from the first conductive layer;

wherein the dielectric film insulates the first conductive layer from the second conductive layer;

wherein the first conductive layer covers the top surface of the substrate except for any area underlying any area surrounded by any first conductive sleeve region; and

wherein the second conductive layer covers the top surface of the substrate except for any area underlying any area surrounded by any second conductive sleeve region.

20. The method of claim 18 comprising forming a capacitor having a first electrode and a second electrode which comprise, respectively, at least one first conductive sleeve region and the corresponding second conductive sleeve region, the first and second electrodes being accessible for electrical contact from another component.

21. A microelectronic component comprising:

a substrate comprising a top surface, a bottom surface, and one or more first through-holes, each first through-hole passing between the top surface and the bottom surface;

one or more conductive vias protruding from the one or more first through-holes to form at each first through-hole a conductive protrusion above the substrate;

for each conductive protrusion protruding from a corresponding first through-hole, a conductive feature comprising a first conductive sleeve region wrapping around the conductive protrusion and extending at least along a segment of the conductive protrusion, the first conductive sleeve region being electrically insulated from the conductive protrusion, the conductive feature comprising a lateral extension extending away from the conductive protrusion at a bottom of the first conductive sleeve region.

22. The microelectronic component of claim 21 wherein the substrate comprises a cavity in the top surface, each conductive protrusion is at least partially located in the cavity;

the substrate further comprises one or more second through-holes, each of which passes between the top surface and the bottom surface outside the cavity; and

the microelectronic component further comprises one or more conductive vias, each of which passes through a corresponding second through-hole and is electrically coupled to a circuit element above the substrate and a circuit element below the substrate.

23. The microelectronic component of claim 1 further comprising, for each conductive protrusion, a corresponding second conductive sleeve region extending at least along said segment of the conductive protrusion and wrapping around the first conductive sleeve region, the second conductive sleeve region being separated from the first conductive sleeve region by a dielectric film.

24. The microelectronic component of claim 21 comprising a conductive layer comprising each first conductive sleeve region;

wherein the conductive layer covers the top surface of the substrate except for any area underlying any area surrounded by any first conductive sleeve region.

25. The microelectronic component of claim 21 wherein each lateral extension laterally surrounds the corresponding conductive protrusion.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0668 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0751 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2015
From: UZOH, CYPRIAN EMEKA; WOYCHIK, CHARLES G.; SITARAM, ARKALGUD R.; SHEN, HONG; SUN, ZHUOWEN; WANG, LIANG; GAO, GUILIAN
To: INVENSAS CORPORATION
Reel/Frame 035245/0851 →