Wafer-level packaging using wire bond wires in place of a redistribution layer
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.
1. A microelectronic package, comprising:
a microelectronic die having a first surface and a second surface opposite the first surface;
a plurality of wire bond wires with proximal ends thereof coupled to the first surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from the first surface of the microelectronic die;
a first pitch of the distal ends being at least a factor of 3 times greater than a second pitch of the proximal ends; and
a portion of the plurality of wire bond wires extending outside a perimeter of the microelectronic die into a fan-out (“FO”) region.
2. The microelectronic package according to claim 1 , further comprising:
a molding material for covering the first surface and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material; and
interconnects coupled to the distal ends of the plurality of wire bond wires.
3. The microelectronic package according to claim 2 , further comprising:
a substrate;
wherein the second surface of the microelectronic die is coupled to a surface of the substrate; and
wherein the molding material covers a portion of the surface of the substrate associated with the FO region.
4. The microelectronic package according to claim 1 , wherein the plurality of wire bond wires include both slanted-out wire bond wires extending to the FO region and slanted-in wire bond wires extending to a fan-in (“FI”) region.
5. The microelectronic package according to claim 1 , wherein:
the first pitch is at least approximately 300 microns; and
the second pitch is at most approximately 100 microns.
6. The microelectronic package according to claim 1 , wherein:
at least a majority of contacts of the microelectronic die are disposed on the first surface of the microelectronic die proximal to the perimeter thereof with no or a minority of the contacts in a central region of the first surface of microelectronic die;
the portion of the plurality of wire bond wires is a first portion thereof; and
a second portion of the plurality of wire bond wires extend over the central region of the first surface of the microelectronic die inside the perimeter of the microelectronic die into a fan-in (“FI”) region.
7. A microelectronic package, comprising:
a microelectronic die having a first surface and a second surface opposite the first surface;
a plurality of wire bond wires with proximal ends thereof coupled to the first surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from the first surface of the microelectronic die;
a first pitch of the distal ends being at least a factor of 3 times greater than a second pitch of the proximal ends; and
a portion of the plurality of wire bond wires extending inside a perimeter of the microelectronic die into a fan-in (“FI”) region as slanted-in wire bond wires extending to the FI region.
8. The microelectronic package according to claim 7 , further comprising:
a molding material for covering the first surface and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to a surface of the molding material; and
interconnects coupled to the distal ends of the plurality of wire bond wires.
9. The microelectronic package according to claim 8 , further comprising:
a substrate;
wherein the second surface of the microelectronic die is coupled to a surface of the substrate; and
wherein the molding material covers a portion of the surface of the substrate associated with the FI region.
10. The microelectronic package according to claim 7 , wherein:
the first pitch is at least approximately 300 microns; and
the second pitch is at most approximately 100 microns.
11. The microelectronic package according to claim 7 , wherein:
at least a majority of contacts of the microelectronic die are disposed on the first surface of the microelectronic die proximal to the perimeter thereof with no or a minority of the contacts in a central region of the first surface of microelectronic die; and
the portion of the plurality of wire bond wires extend over the central region of the first surface of the microelectronic die inside the perimeter of the microelectronic die into the FI region.
12. A package-on-package microelectronic device having the microelectronic package according to claim 7 as a first microelectronic package, the package-on-package device comprising:
the first microelectronic package stacked on a second microelectronic package.
13. A package-on-package microelectronic device having the microelectronic package according to claim 7 as a first microelectronic package, the package-on-package device comprising:
a second microelectronic package stacked on the first microelectronic package.