IP Library Granted Patent US 9,379,060
Granted Patent B2
US 9,379,060 · App. 14/202,162 · Granted Jun 28, 2016

Graphene wiring

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Quick Facts
Patent No.
US 9,379,060
App. No.
14/202,162
Granted
Jun 28, 2016
Kind
B2
Abstract

A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer.

Claims (34)

1. A graphene wiring, comprising:

a substrate;

a catalyst layer on the substrate;

a stack of graphene layers on the catalyst layer; and

a first dopant layer on a first side surface of the stack of graphene layers; and

a second dopant layer on a second side surface of the stack of graphene layers, wherein

an atomic or molecular species is intercalated in the graphene layer,

a bottom side of the stack of graphene layers is on the catalyst layer,

the first dopant layer and the second dopant layer include the atomic or molecular species,

the bottom side of the stack of graphene layers is in physical contact with the catalyst layer,

the dopant layers are in physical contact with the first side surface of the graphene layer and the second side surface of the graphene layer,

each graphene layer of the stack of graphene layers is parallel to the catalyst layer,

a surface of the first dopant layer is in physical contact with each edge of the stack of graphene layers at the first side, and

a surface of the second dopant layer is in physical contact with each edge of the stack of graphene layers at the second side.

2. The wiring according to claim 1 , wherein

a width of the stack of graphene layers is in a range of 3 nm to 30 nm, and

the width of the stack of graphene layers is a distance between the first side surface of the stack of graphene layers and the second side surface of the stack of graphene layers.

3. The wiring according to claim 1 , wherein the atomic or molecular species is at least one selected from the group consisting of Co, Ni, Fe, Ru, Cu, Na, Li, K, Sc, Y, La, Zr, Hf, Ir, and Pt.

4. The wiring according to claim 1 , wherein the stack of graphene layers is multiple layers of graphene sheets including at most 100 layers.

5. The wiring according to claim 1 , wherein a thickness of the first dopant layer of the second dopant layer is in a range of 0.1 nm to 10 nm.

6. The wiring according to claim 1 , wherein the first side surface of the stack of graphene layers and the second side surface of the stack of graphene layers are parallel to a lamination direction of the graphene.

7. The wiring according to claim 1 , wherein the first side surface of the stack of graphene layers is opposite to the second side surface of the stack of graphene layers.

8. The wiring according to claim 1 , wherein the first side surface of the stack of graphene layers and the second side surface of the stack of graphene layers face a surface that extends in a longitudinal direction of the wiring.

9. The wiring according to claim 1 , wherein the stack of graphene layers is sandwiched in between the first side surface of the stack of graphene layers and the second side surface of the stack of graphene layers.

10. The wiring according to claim 1 , wherein

a width of the stack of graphene layers is in a range of 3 nm to 100 nm, and

the width of the stack of graphene layers is a distance between the first side surface of the stack of graphene layers and the second side surface of the stack of graphene layers.

11. The wiring according to claim 1 , wherein an entirety of the bottom side of the stack of graphene layers is in physical contact with the catalyst layer.

12. The wiring according to claim 1 , wherein

the surface of the first dopant layer which is in physical contact with each edge of the stack of graphene layers at the first side is vertical to a surface of the bottom side of the stack of graphene layers, and

the surface of the second dopant layer which is in physical contact with each edge of the stack of graphene layers at the second side is vertical to the surface of the bottom side of the stack of graphene layers.

13. The wiring according to claim 1 , wherein

the surface of the first dopant layer which is in physical contact with an entirety of each edge of the stack of graphene layers at the first side is vertical to a surface of the bottom side of the stack of graphene layers, and

the surface of the second dopant layer which is in physical contact with an entirety of each edge of the stack of graphene layers at the second side is vertical to the surface of the bottom side of the stack of graphene layers.

Assignments (4)
DE-MERGER Recorded Dec 12, 2019
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051260/0291 →
MERGER Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION; K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051262/0776 →
CHANGE OF NAME AND ADDRESS Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 051262/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2014
From: MIYAZAKI, HISAO; SAKAI, TADASHI; KATAGIRI, MASAYUKI; YAMAZAKI, YUICHI; SAKUMA, NAOSHI; SUZUKI, MARIKO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 034019/0765 →