A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.
1. A memory system having three mutually intersecting directions defined as a first direction, a second direction, and a third direction, comprising;
a semiconductor substrate having a principal plane extending in the first direction and the second direction; and
a cell array including plural first lines extending in the third direction, plural second lines extending in the first direction, plural third lines extending in the second direction and provided between said semiconductor substrate and a formation region of said plural first lines, and plural cells formed at intersections of said plural first lines and said plural second lines and having three or more settable physical quantity levels, wherein
said cell array includes plural transistor layers stacked in the third direction and provided between said plural first lines and said plural third lines,
said plural transistor layers include plural transistors operative to electrically connect said plural first lines selectively to one of said plural third lines,
said plural transistors each include a conduction channel composed of polysilicon or an oxide semiconductor and have a gate length extending in the third direction,
said cell array includes a logic circuit containing plural transistors and operative to connect between said first lines and said third lines, and
said plural transistors contained in said logic circuit are formed dispersedly in a first and a second transistor layer adjacent in the third direction of the plural transistor layers.
2. The memory system according to claim 1 , wherein the number of transistors formed in said first transistor layer is smaller than the number of transistors formed in said second switch layer.
3. The memory system according to claim 1 , wherein the conductance of said transistor formed in said first transistor layer is larger than the conductance of said transistor formed in said second transistor layer.
4. The memory system according to claim 1 , wherein the number of transistors belonging to said first transistor layer is smaller than the number of transistors belonging to said second transistor layer among said plural transistors contained in said logic circuit.
5. The memory system according to claim 1 , wherein said transistor has a pillar-shaped conduction channel extending in the third direction and two gates formed so as to sandwich said conduction channel therebetween.
6. The memory system according to claim 1 , wherein said plural cells each include a variable resistance element having a resistance variable in accordance with filament formation by metal ions.