Neuron learning type integrated circuit device using a plurality of synapses, a soma, transistors, a zener diode, and condensers

1. A neuron learning type integrated circuit device, comprising:

a plurality of neuron cell units, each of the plurality of neuron cell units including

a plurality of synapse circuit units, and

a soma circuit unit connected to the plurality of synapse circuit units,

each of the plurality of synapse circuit units including

a first transistor including a first terminal, a second terminal, and a first control terminal, the first terminal being connected to one of a plurality of voltage lines, the first transistor being normally-on,

a second transistor including a third terminal, a fourth terminal, and a second control terminal, the second terminal being connected to the third terminal, the second transistor being normally-off,

a first condenser, one end of the first condenser being connected between the second terminal and the third terminal, and

a control line connected to the first control terminal and the second control terminal,

the soma circuit unit including

a Zener diode including an input terminal and an output terminal, the input terminal being connected to the fourth terminal, and

a second condenser, one end of the second condenser being connected between the fourth terminal and the input terminal.

2. The neuron learning type integrated circuit device according to claim 1 , wherein the level of a signal output from the output terminal is determined according to the difference between a total charge amount storable in the second condenser and an amount of charge stored in the second condenser.

3. The neuron learning type integrated circuit device according to claim 1 , further comprising a delay circuit unit provided between the second terminal and the third terminal, the delay circuit unit being configured to set a time of the first transistor and the second transistor being simultaneously OFF when switching a signal input to the control line ON and OFF.

4. The neuron learning type integrated circuit device according to claim 1 , wherein

the plurality of neuron cell units includes a first neuron cell unit and a second neuron cell unit, the first neuron cell unit being one of the plurality of neuron cell units, the second neuron cell unit being one other of the plurality of neuron cell units, and

the output terminal included in the first neuron cell unit is connected to the first control terminal included in one synapse circuit of the plurality of synapse circuits of the second neuron cell unit.

5. The neuron learning type integrated circuit device according to claim 1 , including a plurality of neuron column units interconnected to each other,

the neuron column unit including a plurality of neuron block units,

the neuron block unit including the plurality of neuron cell units.

6. The neuron learning type integrated circuit device according to claim 1 , further comprising a hash unit, the hash unit being configured to output a hash value based on a hash key and a signal, the signal being input to the control line of each of the plurality of synapse circuits.

7. A neuron learning type integrated circuit device, comprising:

a semiconductor substrate including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the second semiconductor region being arranged with the first semiconductor region; and

a plurality of neuron cell units provided on the semiconductor substrate,

each of the plurality of neuron cell units including

a plurality of synapse circuit units, and

a soma circuit unit connected to the plurality of synapse circuit units,

each of the plurality of synapse circuit units including

a first transistor provided in the second semiconductor region, the first transistor including a first electrode, a second electrode, and a first control electrode, the first electrode being connected to one of a plurality of voltage lines, the first transistor being normally-on,

a second transistor provided in the first semiconductor region, the second transistor including a third electrode, a fourth electrode, and a second control electrode, the third electrode being connected to the second electrode, the second transistor being normally-off,

a first condenser provided between the first semiconductor region and the second semiconductor region, one end of the first condenser being connected between the second electrode and the third electrode, and

a control line connected to the first control electrode and the second control electrode,

the soma circuit unit including

a Zener diode including an input interconnect and an output interconnect, the input interconnect being connected to the fourth electrode, and

a second condenser, one end of the second condenser being connected between the fourth electrode and the input interconnect.

8. The neuron learning type integrated circuit device according to claim 7 , wherein the second condenser includes:

a first plate electrode provided on a first layer, the first transistor and the second transistor being provided in the first layer; and

a second plate electrode provided parallel to the first plate electrode to be separated from the first plate electrode.

9. The neuron learning type integrated circuit device according to claim 8 , wherein the second condenser further includes a floating conductive film provided between the first plate electrode and the second plate electrode.

10. The neuron learning type integrated circuit device according to claim 9 , wherein the second plate electrode has an opening provided in a portion of a region where the second plate electrode and the floating conductive film overlap.

11. The neuron learning type integrated circuit device according to claim 7 , further comprising a delay circuit unit arranged with the first transistor and the second transistor on the semiconductor substrate, the delay circuit unit being configured to set a time of the first transistor and the second transistor being simultaneously OFF when switching a signal input to the control line ON and OFF.

12. The neuron learning type integrated circuit device according to claim 7 , comprising a first neuron cell unit and a second neuron cell unit, the first neuron cell unit being one of the plurality of neuron cell units, the second neuron cell unit being one other of the plurality of neuron cell units,

the output interconnect included in the first neuron cell unit being connected to the first control electrode included in one synapse circuit of the plurality of synapse circuits of the second neuron cell unit.

13. The neuron learning type integrated circuit device according to claim 7 , comprising a first stacked body layer and a second stacked body layer, the first stacked body layer being provided on the semiconductor substrate, the second stacked body layer being provided on the first stacked body layer,

the plurality of neuron cell units being provided in the first stacked body layer, and the plurality of neuron cell units being provided in the second stacked body layer.

14. The neuron learning type integrated circuit device according to claim 13 , further comprising a conductive interconnect layer provided between the first stacked body layer and the second stacked body layer to provide conduction between the neuron cell units included in the first stacked body layer and the neuron cell units included in the second stacked body layer.

15. The neuron learning type integrated circuit device according to claim 7 , comprising a first stacked body layer and a second stacked body layer, the first stacked body layer being provided on a first surface of the semiconductor substrate, the second stacked body layer being provided on a second surface of the semiconductor substrate on a side opposite to the first surface,

the plurality of neuron cell units being provided in the first stacked body layer, and the plurality of neuron cell units being provided in the second stacked body layer,

a via interconnect being provided in the semiconductor substrate to provide conduction between the plurality of neuron cell units included in the first stacked body layer and the plurality of neuron cell units included in the second stacked body layer.