SELF-ALIGNED DOUBLE PATTERNING FOR MEMORY AND OTHER MICROELECTRONIC DEVICES
A semiconductor device is provided. The semiconductor device includes a microelectronic layer, a first mask layer formed on the microelectronic layer having first features separated by first openings, and a second mask layer formed on the first mask layer having second features that are separated by second openings. Each second feature is centrally located on a respective one of the first features. A length each second feature in a dimension is substantially equal to a length of a respective one of the first openings in the dimension.
1 . A semiconductor device, comprising:
a microelectronic layer;
a first mask layer formed on the microelectronic layer having first features separated by first openings; and
a second mask layer formed on the first mask layer having second features that are separated by second openings;
wherein each second feature is centrally located on a respective one of the first features and wherein a length of each second feature in a dimension is substantially equal to a length of a respective one of the first openings in the dimension.
2 . The semiconductor device of claim 1 , wherein the microelectronic layer comprises a layered stack.
3 . The semiconductor device of claim 2 , wherein the layered stack comprises:
a tunneling layer.
4 . The semiconductor device of claim 3 , wherein the layered stack further comprises:
a charge trapping layer that contacts the tunneling layer.
5 . The semiconductor device of claim 4 , wherein the layered stack further comprises:
a dielectric layer that contacts the charge trapping layer.
6 . The semiconductor device of claim 5 , wherein the layered stack further comprises:
a polysilicon layer that contacts the dielectric layer.
7 . The semiconductor device of claim 1 , further comprising:
a film that fills the first openings and the second openings.
8 . The semiconductor device of claim 1 , further comprising:
a photoresist mask layer that contacts the second mask layer.
9 . The semiconductor device of claim 8 , wherein the photoresist mask layer includes third features separated by third openings, wherein each third feature contacts a respective one of the second features, and Wherein each third opening coincides with a respective one of the second openings.
10 . The semiconductor device of claim 9 , further comprising:
spacers, wherein each spacer contacts a sidewall portion of a respective one of the third features and a sidewall portion of a respective one of the second features.
11 . The semiconductor device of claim 10 , wherein a height of each of the spacers relative to the first mask layer is substantially equal to a height of the respective one of the third features relative to the first mask layer.
12 . The semiconductor device of claim 1 , wherein the first mask layer comprises a silicon nitride layer.
13 . The semiconductor device of claim 1 , wherein the first mask layer comprises a silicon-oxy-nitride layer.
14 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a NAND memory.
15 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a NOR memory.
16 . The semiconductor device of claim 1 , wherein the length of each second feature is substantially equal to one-third of a length of a respective one of the first features.
17 . The semiconductor device of claim 1 , wherein the second mask layer comprises a polysilicon material.