Granted Patent B2

US 9,268,351 · App. 14/208,180 · Granted Feb 23, 2016

Abstract

Claims (24)

1. A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration:

wherein the first field effect transistor is a depletion mode transistor having a leakage current in operation;

wherein the second field effect transistor comprises an inherent drain to source resistance and additional drain to source resistance arranged in parallel to the first drain to source resistance, the second additional drain to source resistance arranged such that in operation current through the additional resistance matches the leakage current of the first field effect transistor; and

whereby a gate of the first field effect transistor is connected to the drain of the second field effect transistor; and

wherein the second additional drain to source resistance is a resistive divider, and comprises at least two resistances connected as a voltage divider having a common node, wherein the common node of the voltage divider is connected to the gate of a third field effect transistor.

2. The semiconductor device of claim 1 , wherein the leakage current is a drain source leakage current.

3. The semiconductor device of claim 1 , wherein the second additional drain source resistance is an active clamp.

4. The semiconductor device of claim 1 , wherein the second additional drain to source resistance is integrated with the second field effect transistor.

5. The semiconductor device of claim 1 , wherein the first field effect transistor is a High Electron Mobility Transistor or a Junction Gate Field Effect Transistor.

6. The semiconductor device of claim 1 , wherein the second and third field effect transistors are n-channel transistors.

7. The semiconductor device of claim 1 , wherein the first, second and third field effect transistors are integrated onto a single die.

8. A power factor correction circuit comprising the semiconductor device as claimed in claim 1 .

9. A power supply comprising the power factor correction circuit of claim 8 .

10. A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration:

wherein the first field effect transistor is a depletion mode transistor having a leakage current in operation;

wherein the second field effect transistor comprises an inherent drain to source resistance and additional drain to source resistance arranged in parallel to the first drain to source resistance, the second additional drain to source resistance arranged such that in operation current through the additional resistance matches the leakage current of the first field effect transistor; and

whereby a gate of the first field effect transistor is connected to the drain of the second field effect transistor; and

wherein the second additional drain to source resistance is integrated by deep trench isolation.

11. A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration:

wherein the first field effect transistor is a depletion mode transistor having a leakage current in operation;

wherein the second field effect transistor comprises an inherent drain to source resistance and additional drain to source resistance arranged in parallel to the first drain to source resistance, the second additional drain to source resistance arranged such that in operation current through the additional resistance matches the leakage current of the first field effect transistor;

whereby a gate of the first field effect transistor is connected to the drain of the second field effect transistor; and

wherein an additional capacitance arranged in parallel across drain and source of the second field effect transistor.

12. The semiconductor device of claim 11 , wherein the additional capacitance is arranged to increase the junction capacitance of the second field effect transistor.

Assignments (12)