Contact silicide having a non-angular profile
A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.
1. A method of fabricating a semiconductor device, comprising:
providing a substrate having a source/drain region and a dielectric layer over the source/drain region;
forming an opening in the dielectric layer, wherein the opening exposes the source/drain region;
performing an implantation process through the opening to form an amorphous portion in the source/drain region, wherein the implantation process is performed such that the amorphous portion has substantially straight sidewalls and a rounded bottom surface;
depositing a metal in the opening, the metal being deposited on the amorphous portion; and
annealing the metal to facilitate a reaction between the metal and the amorphous portion, thereby forming a metal silicide in the source/drain region, wherein the metal silicide is formed substantially below an upper surface of the substrate and assumes a cross-sectional view geometric profile of the amorphous portion.
2. The method of claim 1 , wherein the performing the implantation process comprises performing a cold implantation process, and wherein the cold implantation process is performed such that the amorphous portion is formed entirely within the source/drain region.
3. The method of claim 2 , wherein the cold implantation process is performed at a temperature in a range from −60 degrees Celsius to −100 degrees Celsius.
4. The method of claim 1 , further comprising:
performing, after the annealing, an etching process to remove un-reacted portions of the metal;
performing a further annealing process after the etching process; and
forming a contact element in the opening and on the metal silicide after the further annealing process.
5. The method of claim 1 , further comprising: before the forming of the opening, forming a gate structure over the substrate and forming the source/drain region by implanting a first region adjacent the gate structure, wherein the amorphous portion is completely in the first region.
6. The method of claim 1 , wherein the annealing comprises a spike annealing process.
7. The method of claim 1 , wherein the implantation process is performed using carbon ions or nitrogen ions.
8. The method of claim 1 , wherein the implantation process is performed using an implantation energy ranging from 1 keV to 100 keV.
9. The method of claim 1 , wherein the straight sidewalls of the metal silicide are formed to be flush with sidewalls of the opening.
10. A method, comprising:
providing a substrate having a source/drain region and a dielectric layer over the source/drain region;
forming an opening in the dielectric layer, wherein the opening exposes the source/drain region;
performing an ion implantation process through the opening to form an amorphous portion in the source/drain region, the amorphous portion having substantially straight sidewalls and a rounded bottom surface, wherein at least one of the substantially straight sidewalls of the amorphous portion is flush with a sidewall of the opening in the dielectric layer;
depositing a metal on the amorphous portion; and
annealing the metal, thereby forming a metal silicide feature in the amorphous portion, wherein the metal silicide feature is formed substantially below an upper surface of the substrate, and wherein the metal silicide feature has substantially straight sidewalls and a bottom surface that coincide with the substantially straight sidewalls and the rounded bottom surface of the amorphous portion, respectively.
11. The method of claim 10 , wherein the substrate comprises silicon and the amorphous portion comprises amorphous silicon, and wherein the amorphous portions is formed to be surrounded by the source/drain region.
12. The method of claim 10 , wherein the ion implantation process is performed at a temperature ranging from −60 degrees Celsius to −100 degrees Celsius.
13. The method of claim 10 , wherein the annealing of the metal has a spike temperature profile.
14. The method of claim 13 , wherein the spike temperature profile has a peak temperature ranging from 200 degrees Celsius to 300 degrees Celsius and the peak temperature is maintained for a duration ranging from few milliseconds to few seconds.
15. The method of claim 10 , further comprising:
etching portions of the metal above the metal silicide feature; and
performing another annealing process to lower a resistivity of the metal silicide feature, wherein the another annealing process uses a different temperature profile than the annealing of the metal.
16. The method of claim 10 , wherein the ion implantation process is performed using an implantation energy ranging from 1 keV to 100 keV.
17. A method, comprising:
providing a substrate having a source/drain region and a dielectric layer over the source/drain region;
forming an opening through the dielectric layer, thereby exposing the source/drain region;
performing a cryo-implantation process through the opening to form an amorphous portion entirely within the source/drain region, the amorphous portion being formed to have linear side surfaces and a curved bottom surface, wherein the linear surfaces are perpendicular to a surface of the substrate, and wherein the linear surfaces are aligned with sidewalls of the dielectric layer that define the opening;
depositing a metal on the amorphous portion;
performing a first annealing process, thereby forming a metal silicide feature in place of the amorphous portion, the metal silicide feature being formed substantially below an upper surface of the substrate and assuming a geometric profile of the amorphous portion; and
performing a second annealing process to lower a resistivity of the metal silicide feature, wherein the first annealing process is performed using a different temperature profile than the second annealing process.
18. The method of claim 17 , wherein the first annealing process has a peak temperature ranging from 200 degrees Celsius to 300 degrees Celsius and the peak temperature is maintained for a duration ranging from few milliseconds to few seconds.
19. The method of claim 17 , wherein:
the source/drain region comprises silicon;
the cryo-implantation process uses ions of silicon, germanium, xenon, carbon, arsenic, or nitrogen; and
the cryo-implantation process uses an implantation energy ranging from 1 keV to 100 keV.
20. The method of claim 17 , wherein at least one of the first annealing process and the second annealing process comprises a spike annealing process, and wherein the amorphous portion is formed without protruding laterally underneath the dielectric layer.