Flip-flop circuit and semiconductor apparatus using the same
A flip-flop circuit may include: a latch unit configured to latch an input signal in response to a clock signal; and a timing control unit configured to delay a signal provided from the latch unit by a predetermined time regardless of the clock signal.
1. A flip-flop circuit comprising:
a latch unit configured to latch an input signal in response to a clock signal; and
a timing control unit configured to generate a delay signal by delaying a signal provided from the latch unit by a predetermined time regardless of the clock signal and output the delay signal as a final output data of the flip-flop circuit,
wherein the timing control unit comprises a transmission switching element configured to be driven by first and second bias voltages and delay the output signal of the latch unit.
2. The flip-flop circuit according to claim 1 , further comprising:
an input unit configured to latch an initial input signal in response to the clock signal; and
a driving unit configured to latch the signal provided from the input unit in response to the clock signal and output the latched signal as the input signal.
3. The flip-flop circuit according to claim 2 , wherein the input unit latches the initial input signal in synchronization with a first phase of the clock signal, the driving unit latches a signal provided from the input unit in synchronization with a second phase of the clock signal, and the latch unit latches the input signal in synchronization with the first phase of the clock signal.
4. A semiconductor apparatus comprising a plurality of flip-flop circuits coupled in series,
wherein each of the flip-flop circuits comprises:
a latch unit configured to latch an input signal in response to a clock signal; and
a timing control unit configured to generate a delay signal by delaying a signal provided from the latch unit by a preset time regardless of the clock signal and output the delay signal as a final output data of the flip-flop circuit,
wherein the timing control unit comprises a transmission switching element configured to be driven by first and second bias voltages and delay the output signal of the latch unit.