Barrier structure for copper interconnect

1. A method, comprising:

forming a first dielectric layer overlying a substrate;

forming an opening in the first dielectric layer;

forming a metal-containing layer overlying the opening in the first dielectric layer, the metal-containing layer comprising manganese (Mn);

forming a conformal protective layer overlying the metal-containing layer;

filling a conductive layer in the opening;

forming a second dielectric layer overlying the conductive layer and the first dielectric layer; and

after forming the second dielectric layer, performing a thermal process to begin forming a MnOx barrier layer underlying the metal-containing layer such that a bottommost surface of the MnOx barrier layer is substantially level with a bottommost surface of the metal-containing layer, the MnOx barrier layer having a weight ratio of manganese to oxygen from about 0.1 to about 10.

2. The method of claim 1 , wherein the metal-containing layer is a copper-containing layer.

3. The method of claim 1 , wherein the metal-containing layer comprising Mn is a CuMn layer.

4. The method of claim 3 , wherein a ratio of manganese to copper in the CuMn layer ranges from about 0.02% to about 5%.

5. The method of claim 3 , wherein the CuMn layer has a face center cubic (FCC) crystal structure.

6. The method of claim 1 , wherein the metal-containing layer has a thickness ranging from about 20 Angstroms to about 200 Angstroms.

7. The method of claim 1 , wherein the conformal protective layer is a cobalt (Co) layer, a ruthenium (Ru) layer, or combinations thereof.

8. The method of claim 7 , wherein the conformal protective layer has a thickness ranging from about 10 Angstroms to about 50 Angstroms.

9. The method of claim 1 , wherein the conformal protective layer is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

10. The method of claim 1 , further comprising forming a seed layer in the opening prior to forming the conductive layer.

11. The method of claim 1 , wherein the MnOx barrier layer is formed by reacting Mn in the metal-containing layer and oxygen in the first dielectric layer.

12. A method, comprising:

forming a dielectric layer overlying a substrate;

forming an opening in the dielectric layer;

forming a copper manganese (CuMn) layer overlying the opening in the dielectric layer;

forming a conformal cobalt (Co) or ruthenium (Ru) layer overlying the CuMn layer;

filling a conductive layer in the opening;

performing a chemical mechanical polishing (CMP) process to remove portions of the conductive layer outside the opening; and

after performing the CMP process, performing a thermal process to form a MnOx barrier layer underlying the CuMn layer such that at least a portion of the CuMn layer contacts the substrate, the MnOx barrier layer having a weight ratio of manganese to oxygen from about 0.1 to about 10.

13. The method of claim 12 , wherein the CuMn layer has a thickness ranging from about 20 Angstroms to about 200 Angstroms.

14. The method of claim 12 , wherein a ratio of manganese to copper in the CuMn layer ranges from about 0.02% to about 5%.

15. The method of claim 12 , wherein the conformal Co/Ru layer has a thickness ranging from about 10 Angstroms to about 50 Angstroms and is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

16. The method of claim 12 , wherein the MnOx barrier layer is formed by reacting the Mn in the CuMn layer and oxygen in the dielectric layer.

17. The method of claim 12 , wherein the CuMn layer has a face center cubic (FCC) crystal structure.

18. A method, comprising:

forming a dielectric layer overlying a semiconductor substrate;

patterning the dielectric layer to form a trench therein;

lining the trench with a metal-containing layer, the metal-containing layer comprising an additive metal element;

forming a conformal protective layer on the metal-containing layer;

filling a conductive layer in the trench;

removing portions of the conductive layer overfilling the trench; and

forming an etch stop layer overlying the conductive layer and the dielectric layer; and

after removing the portions of the conductive layer, heating the metal-containing layer to form a metal oxide barrier layer underlying the metal-containing layer such that the metal-containing layer directly contacts at least a portion of the semiconductor substrate, the metal oxide barrier layer comprising an oxide of the additive metal element.

19. The method of claim 18 wherein heating the metal-containing layer comprises performing an annealing process.

20. The method of claim 19 wherein the annealing process is performed at a temperature of from about 137 degrees Celsius to about 600 degrees Celsius.