Non-volatile memory which can increase the operation window
View Patent ↗A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.
1. A non-volatile memory comprising:
a plurality of rows of memory cells;
a plurality of bit lines coupled to the plurality of rows of memory cells configured to access data to the plurality of rows of memory cells;
a plurality of word lines each coupled to a corresponding row of memory cells; and
a decoder coupled to the plurality of word lines configured to enable at least two rows of memory cells of the plurality of rows of memory cells.
2. The non-volatile memory of claim 1 wherein the decoder comprises:
an inverter, comprising:
an input terminal configured to receive an optional signal; and
an output terminal;
a first NAND gate, comprising:
a first input terminal configured to receive a decoded address signal;
a second input terminal coupled to the output terminal of the inverter; and
an output terminal coupled to a first word line of the plurality of word lines; and
a second NAND gate, comprising:
a first input terminal coupled to the output terminal of the first NAND gate;
a second input terminal coupled to the output terminal of the inverter; and
an output terminal coupled to a second word line of the plurality of word lines.
3. The non-volatile memory of claim 1 wherein the decoder comprises:
a first inverter, comprising:
an input terminal configured to receive an optional signal; and
an output terminal;
a first NAND gate, comprising:
a first input terminal configured to receive a first decoded address signal;
a second input terminal coupled to the output terminal of the first inverter; and
an output terminal;
a second NAND gate, comprising:
a first input terminal configured to receive a second decoded address signal;
a second input terminal coupled to the output terminal of the first inverter; and
an output terminal;
a third NAND gate, comprising:
a first input terminal coupled to the output terminal of the first NAND gate;
a second input terminal coupled to the output terminal of the first inverter; and
an output terminal;
a fourth NAND gate, comprising:
a first input terminal coupled to the output terminal of the second NAND gate;
a second input terminal coupled to the output terminal of the first inverter; and
an output terminal;
a fifth NAND gate, comprising:
a first input terminal coupled to the output terminal of the third NAND gate;
a second input terminal coupled to the output terminal of the fourth NAND gate; and
an output terminal;
a sixth NAND gate, comprising:
a first input terminal coupled to the output terminal of the first NAND gate;
a second input terminal coupled to the output terminal of the fourth NAND gate; and
an output terminal;
a seventh NAND gate, comprising:
a first input terminal coupled to the output terminal of the third NAND gate;
a second input terminal coupled to the output terminal of the second NAND gate; and
an output terminal;
an eighth NAND gate, comprising:
a first input terminal coupled to the output terminal of the first NAND gate;
a second input terminal coupled to the output terminal of the second NAND gate; and
an output terminal;
a second inverter, comprising:
an input terminal coupled to the output terminal of the fifth NAND gate; and
an output terminal coupled to a first word line of the plurality of word lines;
a third inverter, comprising:
an input terminal coupled to the output terminal of the sixth NAND gate; and
an output terminal coupled to a second word line of the plurality of word lines;
a fourth inverter, comprising:
an input terminal coupled to the output terminal of the seventh NAND gate; and
an output terminal coupled to a third word line of the plurality of word lines; and
a fifth inverter, comprising:
an input terminal coupled to the output terminal of the eighth NAND gate; and
an output terminal coupled to a fourth word line of the plurality of word lines.
4. A method for controlling a non-volatile memory, the non-volatile memory comprising a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells, and a plurality of word lines each coupled to a corresponding row of memory cells, the method comprising:
enabling a first word line of two word lines according to an optional signal and at least one decoded address signal;
accessing data to a row of memory cells coupled to the first word line through the bit lines while the first word line is enabled;
enabling the two word lines when the optional signal has a predetermined logic value; and
accessing data to two rows of memory cells coupled to the two word lines through the bit lines while the two word lines are enabled.
5. A method for controlling a non-volatile memory, the non-volatile memory comprising a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells, and a plurality of word lines each coupled to a corresponding row of memory cells, the method comprising:
enabling a first word line of four word lines according to an optional signal and two decoded address signals;
accessing data to a row of memory cells coupled to the first word line through the bit lines while the first word line is enabled;
enabling the four word lines when the optional signal has a predetermined logic value; and
accessing data to four rows of memory cells coupled to the four word lines through the bit lines while the four word lines are enabled.
6. A method for controlling a non-volatile memory, the non-volatile memory comprising a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells, and a plurality of word lines each coupled to a corresponding row of memory cells of the plurality of rows of memory cells, the method comprising:
enabling the plurality of word lines when an optional signal has a predetermined logic value; and
accessing data to the plurality of rows of memory cells coupled to the plurality of word lines through the bit lines while the plurality of word lines are enabled.
7. The method of claim 6 wherein the plurality of rows of memory cells is m rows of memory cells where m is an integer greater than 1.
8. The method of claim 6 wherein the plurality of rows of memory cells is 2 n rows of memory cells where n is a positive integer.