Cascoded semiconductor devices with gate bias circuit
View Patent ↗The invention provides a cascode transistor circuit with a depletion mode transistor and a switching device. A gate bias circuit is connected between the gate of the depletion mode transistor and the low power line. The gate bias circuit is adapted to compensate the forward voltage of a diode function of the switching device. The depletion mode transistor and the gate bias circuit are formed as part of an integrated circuit.
1. A cascode transistor circuit comprising:
a first, depletion mode transistor having its drain connected to a high power line;
a switching device connected between the source of the first transistor and a low power line, the switching device comprising a diode function for enabling reverse current flow in the first transistor; and
a gate bias circuit connected between the gate of the first transistor and the low power line, the gate bias circuit being adapted to compensate the forward voltage of the diode function of the switching device such that a forward voltage of the gate of the first transistor is increased for reverse current flows, wherein the gate bias circuit comprises first and second diodes connected in parallel and in opposing directions with the cathode of the first diode connected directly to the anode of the second diode and the cathode of the second diode connected directly to the anode of the first diode;
wherein the first transistor and the gate bias circuit are formed as part of an integrated circuit.
2. A circuit as claimed in claim 1 , wherein the first, depletion mode transistor comprises a gallium nitride or silicon carbide transistor.
3. A circuit as claimed in claim 1 , wherein the first, depletion mode transistor comprises a high electron mobility transistor.
4. A circuit as claimed in claim 1 , wherein the switching device comprises a silicon MOSFET with its drain connected to the source of the first transistor and its source connected to the low power line, the silicon MOSFET comprising a body diode.
5. A circuit as claimed in claim 4 , wherein the silicon MOSFET comprises a trench MOS transistor.
6. A circuit as claimed in claim 1 , formed as a packaged device, with a first connection from the first transistor drain to a first package terminal, a second connection from the switching device to a second package terminal, wherein one of the package terminals comprises a die attach pad terminal.
7. A circuit arrangement comprising:
a cascode transistor circuit as claimed in claim 1 .
8. A device comprising a circuit arrangement as claimed in claim 7 , wherein the device comprises:
a power supply; or
a power factor correction circuit; or
an inverter circuit; or
a switched mode power converter circuit.
9. A cascode transistor circuit comprising:
a depletion mode transistor having its drain connected to a high power line;
a switching device connected between the source of the depletion mode transistor and a low power line, the switching device comprising a diode function for enabling reverse current flow in the depletion mode transistor; and
a gate bias circuit connected between the gate of the depletion mode transistor and the low power line, the gate bias circuit being adapted to compensate the forward voltage of the diode function of the switching device such that a forward voltage of the gate of the depletion mode transistor is increased for reverse current flows;
wherein the depletion mode transistor and the gate bias circuit are formed on the same die;
wherein the gate bias circuit comprises first and second diodes connected in parallel and in opposing directions with the cathode of the first diode connected directly to the anode of the second diode and the cathode of the second diode connected directly to the anode of the first diode;
wherein the depletion mode transistor comprises a gallium nitride or silicon carbide transistor;
wherein the switching device comprises a silicon MOSFET with its drain connected to the source of the depletion mode transistor and its source connected to the low power line.
10. A circuit arrangement comprising:
a cascode transistor circuit as claimed in claim 9 .
11. A circuit arrangement as claimed in claim 10 , formed as a packaged device, with a first connection from the drain of the depletion mode transistor to a first package terminal, a second connection from the switching device to a second package terminal, wherein one of the package terminals comprises a die attach pad terminal.
12. A cascode transistor circuit comprising:
a depletion mode transistor having its drain connected to a high power line, wherein the depletion mode transistor comprises a gallium nitride or silicon carbide transistor;
a switching device connected between the source of the depletion mode transistor and a low power line, the switching device comprising a diode function for enabling reverse current flow in the depletion mode transistor; and
a gate bias circuit connected between the gate of the depletion mode transistor and the low power line and comprising first and second diodes connected in parallel and in opposing directions with the cathode of the first diode connected directly to the anode of the second diode and the cathode of the second diode connected directly to the anode of the first diode, the gate bias circuit being adapted to compensate the forward voltage of the diode function of the switching device such that a forward voltage of the gate of the depletion mode transistor is increased for reverse current flows;
wherein the depletion mode transistor and the gate bias circuit are formed on the same die.