Embedded system boot from a storage device
A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers. Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness. Through the use of the Power-On Reset Sequencer module, integrity of program code and user data used in the boot up process can be verified thus providing a resilient boot up sequence. The present invention provides a mechanism for booting up a system using a minimum amount of nonvolatile memory. This method also enables the embedded system to initialize all configuration registers even before any of the CPUs of the system is brought out of reset. The embedded system consists of multiple controller chips or a single controller chip. The embedded system can have a single or multiple central processing units.
1. An apparatus, comprising:
an embedded system comprising one or more processors, a reset controller, a storage device controller, one or more direct memory access (DMA) controllers, a random access memory (RAM) and a memory controller, a nonvolatile memory and a nonvolatile memory controller, a debug interface, and
a power-on reset (POR) sequencer configured to detect, in the nonvolatile memory, a descriptor used in a boot process and configured to copy the descriptor from the nonvolatile memory to the RAM,
wherein the POR sequencer facilitates a boot process and verifies an integrity of loaded data and code in the RAM,
wherein the descriptor comprises a POR sequencer descriptor, and wherein the POR sequencer uses the POR sequencer descriptor which is a preassembled descriptor that is stored in the nonvolatile memory,
wherein the POR sequencer descriptor includes register information and DMA controller descriptors, and
wherein the POR sequencer reads and uses the register information to update configuration registers of the embedded system.
2. The apparatus of claim 1 ,
wherein the one or more processors reads and executes firmware;
wherein the reset controller maintains reset states of all devices of the embedded system;
wherein the storage device controller provides an interface to a storage device;
wherein the one or more direct memory access controllers initiates and tracks data transfers;
wherein the RAM is used to temporarily store firmware;
wherein the memory controller provides an interface to the RAM;
wherein the nonvolatile memory comprises a read only memory (ROM);
wherein the ROM is used to store data used by the POR sequencer in a boot process of the embedded system;
wherein the debug interface is used to pre-program the ROM and the storage device with data and code; and
wherein the POR sequencer controls the boot process of the embedded system.
3. The apparatus of claim 1 , wherein the POR sequencer loads DMA descriptors to the DMA controllers.
4. The apparatus of claim 1 , wherein the POR sequencer processes a linked-list of data structures in order to increase an amount of register information and DMA descriptors that are processed by the POR sequencer.
5. The apparatus of claim 1 , further comprising: a CPU bus in the embedded system.
6. An apparatus, comprising:
an embedded system comprising one or more processors, a reset controller, a storage device controller, one or more direct memory access (DMA) controllers, a random access memory (RAM) and a memory controller, a nonvolatile memory and a nonvolatile memory controller, a debug interface, and
a power-on reset (POR) sequencer, wherein the POR sequencer uses a POR sequencer descriptor which is a preassembled descriptor that is stored in the nonvolatile memory,
wherein the POR sequencer descriptor includes register information and DMA controller descriptors, and
wherein the POR sequencer reads and uses the register information to update configuration registers of the embedded system.
7. The apparatus of claim 6 ,
wherein the one or more processors reads and executes firmware;
wherein the reset controller maintains reset states of all devices of the embedded system;
wherein the storage device controller provides an interface to a storage device;
wherein the one or more direct memory access controllers initiates and tracks data transfers;
wherein the RAM is used to temporarily store firmware;
wherein the memory controller provides an interface to the RAM;
wherein the nonvolatile memory comprises a read only memory (ROM);
wherein the ROM is used to store data used by the POR sequencer in a boot process of the embedded system;
wherein the debug interface is used to pre-program the ROM and the storage device with data and code; and
wherein the POR sequencer controls the boot process of the embedded system.
8. The apparatus of claim 6 , wherein the POR sequencer loads DMA descriptors to the DMA controllers.
9. The apparatus of claim 6 , wherein the POR sequencer facilitates a boot process and verifies an integrity of loaded data and code in the RAM.
10. The apparatus of claim 6 , wherein the POR sequencer processes a linked-list of data structures in order to increase an amount of register information and DMA descriptors that are processed by the POR sequencer.
11. The apparatus of claim 6 , further comprising: a CPU bus in the embedded system.
12. An article of manufacture, comprising:
a non-transitory computer-readable medium having stored thereon instructions to permit an apparatus to perform a method comprising:
detecting in a nonvolatile memory in the apparatus, by a power-on reset (POR) sequencer, a descriptor used in a boot process and copying, by the POR sequencer, the descriptor from the nonvolatile memory to a random access memory (RAM), and
facilitating, by the POR sequencer, a boot process and verifying, by the POR sequencer, an integrity of loaded data and code in the RAM,
wherein the descriptor comprises a POR sequencer descriptor, and wherein the POR sequencer uses the POR sequencer descriptor which is a preassembled descriptor that is stored in the nonvolatile memory,
wherein the POR sequencer descriptor includes register information and DMA controller descriptors, and
wherein the POR sequencer reads and uses the register information to update configuration registers of the embedded system.
13. The article of manufacture of claim 12 ,
wherein the apparatus comprises an embedded system comprising one or more processors, a reset controller, a storage device controller, one or more direct memory access (DMA) controllers, the random access memory (RAM) and a memory controller, the nonvolatile memory and a nonvolatile memory controller, a debug interface, and the POR sequencer;
wherein the one or more processors reads and executes firmware;
wherein the reset controller maintains reset states of all devices of the embedded system;
wherein the storage device controller provides an interface to a storage device;
wherein the one or more direct memory access controllers initiates and tracks data transfers;
wherein the RAM is used to temporarily store firmware;
wherein the memory controller provides an interface to the RAM;
wherein the nonvolatile memory comprises a read only memory (ROM);
wherein the ROM is used to store data used by the POR sequencer in a boot process of the embedded system;
wherein the debug interface is used to pre-program the ROM and the storage device with data and code; and
wherein the POR sequencer controls the boot process of the embedded system.