Debug control circuit
View Patent ↗A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation. The method and apparatus set, with the control circuit, a second operation mode in which a split transaction is not issued and transfer, with the control circuit, the command to a processing unit via the bus in response to the command transfer request when in the second operation mode where after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.
1. An apparatus comprising:
a command register to store a command; and
a control circuit to:
set a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation and set a second operation mode in which the split transaction is not issued; and
transfer the command to a processing unit, via the bus, in response to the command transfer request when in the second operation mode, wherein, after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.
2. The apparatus of claim 1 , wherein the command comprises a branching command to a memory address.
3. The apparatus of claim 2 , wherein, when in the second operation mode, the control circuit transfers the branching command to the processing unit in response to the command transfer request.
4. The apparatus of claim 1 , wherein the control circuit receives the command transfer request when the processing unit executes a break factor command in a user program.
5. The apparatus of claim 1 , wherein the command comprises a debug command and the control circuit transmits the debug command to the processing unit, via the bus, during the time period.
6. The apparatus of claim 5 , wherein the control circuit restarts a halted user program executed by the processing unit after execution of the debug command.
7. A method comprising:
storing a command in a command register;
setting, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation;
setting, with the control circuit, a second operation mode in which a split transaction is not issued; and
transferring, with the control circuit, the command to a processing unit, via the bus, in response to the command transfer request when in the second operation mode, wherein, after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.
8. The method of claim 7 , further comprising:
receiving the command transfer request when the processing unit executes a break factor command in a user program.
9. The method of claim 7 , wherein the storing comprises storing a branching command to a memory address.
10. The method of claim 9 , wherein setting the second operation mode comprises transferring the branching command to the processing unit in response to the command transfer request.
11. The method of claim 7 , wherein the command comprises a debug command, and wherein the transferring comprises transmitting the debug command to the processing unit, via the bus, during the time period.
12. The method of claim 7 , wherein the command comprises a debug command, and the method further comprising:
restarting a halted user program executed by the processing unit after execution of the debug command.
13. A system comprising:
a bus;
a processing unit; and
a debug circuit comprising:
a command register to store a command; and
a control circuit to:
set a first operation mode associated with a split transaction for freeing the bus in a time period between a command transfer request and a command transfer operation and set a second operation mode in which a split transaction is not issued; and
transfer the command to a processing unit, via the bus, in response to the command transfer request when in the second operation mode, wherein, after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.
14. The system of claim 13 , wherein the command comprises a branching command to a memory address.
15. The system of claim 14 , wherein, when in the second operation mode, the control circuit transfers the branching command to the processing unit in response to the command transfer request.
16. The system of claim 13 , wherein the control circuit receives the command transfer request when the processing unit executes a break factor command in a user program.
17. The system of claim 13 , wherein the command comprises a debug command and the control circuit transmits the debug command to the processing unit, via the bus, during the time period.
18. The system of claim 17 , wherein the control circuit is restarts a halted user program executed by the processing unit after execution of the debug command.
19. An integrated circuit comprising:
a bus;
a processing unit to execute a user program; and
a debugging circuit coupled to the bus, the debugging circuit comprising a command register,
wherein, when the processing unit executes a command including a break factor in the user program,
the processing unit to halt the execution of the user program and issue a command transfer request to the debugging circuit,
the debugging circuit to perform a split response for freeing a use right of the bus from the processing unit,
the processing unit to free the use right of the bus and enter a wait state,
the debugging circuit to prepare a debugging command in the command register and transfer the debugging command to the processing unit via the bus, and
the processing unit to restart the execution of the halted user program after execution of the debugging command,
wherein the debugging circuit to be set in one of a first operation mode in which the split response is made and a second operation mode in which the split response is not made,
in an initial state, a command for branching to a specific address is to be stored in the command register of the debugging circuit,
when the debugging circuit is set in the second operation mode, the debugging circuit to immediately transfer the command for branching to the specific address to the processing unit in response to the command transfer request, and
wherein after the processing unit executes the command for branching to the specific address and a command that begins from the specific address, and issues a subsequent command transfer request to the debugging circuit, the debugging circuit to perform the split response even when the debugging circuit is set in the second operation mode.
20. A debugging command control method for use with an integrated circuit, the method comprising:
a bus,
a processing unit to execute a user program, and
a debugging circuit coupled to the bus, the debugging circuit to transfer a command to the processing unit via the bus in response to a command transfer request from the processing unit, the debugging command control method comprising:
halting the execution of the user program and transmitting the command transfer request from the processing unit to the debugging circuit;
sending, in response to the command transfer request, a split response from the debugging circuit to the processing unit for freeing a use right of the bus from the processing unit;
freeing the use right of the bus from the processing unit in response to the split response;
preparing a debugging command in the command register and transferring the debugging command to the processing unit via the bus;
executing the halted user program after executing the debugging command;
operating the debugging circuit in one of a first operation mode in which the split response is made and a second operation mode in which the split response is not made;
in an initial state, storing a command for branching to a specific address in the command register of the debugging circuit;
when the debugging circuit is set in the second operation mode, the debugging circuit to immediately transfer the command for branching to the specific address to the processing unit in response to the command transfer request; and
after the processing unit executes the command for branching to the specific address and a command that begins from the specific address, and issues a subsequent command transfer request to the debugging circuit, the debugging circuit to perform the split response even when the debugging circuit is set in the second operation mode.