Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof

1. A refresh method of a volatile memory device, the method comprising:

detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased;

outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reaches a reference value; and

performing a refresh operation on the second memory area in response to the alert signal.

2. The method of claim 1 , wherein performing the refresh operation on the second memory area includes receiving a refresh command provided from a memory controller in response to the alert signal.

3. The method of claim 1 , wherein performing the refresh operation on the second memory area comprises:

performing a refresh operation on memory cells connected to a first word line of the second memory area; and

performing a refresh operation on memory cells connected to a second word line of the second memory area,

wherein the second memory area is located adjacent to the first memory area.

4. The method of claim 1 , wherein performing the refresh operation on the second memory area includes:

receiving a first refresh command provided from a memory controller in response to the alert signal; and

receiving a second refresh command subsequently to the first refresh command from the memory controller.

5. The method of claim 4 , wherein performing the refresh operation on the second memory area comprises:

performing a refresh operation on memory cells connected to a first word line of the second memory area in response to the first refresh command; and

performing a refresh operation on memory cells connected to a second word line of the second memory area in response to the second refresh command,

wherein the second memory area is located adjacent to the first memory area.

6. The method of claim 1 , further comprising:

storing an address related to the first memory area or the second memory area in a register,

wherein performing the refresh operation on the second memory area includes outputting the address by receiving a mode register read command from the outside of the volatile memory device.

7. The method of claim 6 , further comprising:

after receiving the mode register read command, receiving at least a one-time refresh command provided from a memory controller.

8. The method of claim 1 , wherein the volatile memory device is a first chip, and outputting the alert signal from the volatile memory device to the outside of the volatile memory device includes outputting the alert signal from the first chip to a second chip.

9. The method of claim 1 , wherein the alert signal is outputted as a pulse signal having a specific pulse width.

10. The method of claim 1 , wherein

the alert signal is shifted from a first logic level to a second logic level when the detected number of disturbances reaches the reference value, and is shifted from the second logic level to the first logic level when the refresh operation on the second memory area is completed.

11. The method of claim 1 , wherein the number of disturbances that affects the second memory area corresponds to a number of active commands on the first memory area.

12. A volatile memory device comprising:

a cell array including a plurality of DRAM cells;

a disturbance detector configured to count a number of accesses to a first memory area of the cell array and generate a detect signal when the number of the counted accesses reaches a reference value;

a refresh control logic configured to, in response to the detect signal, perform a refresh operation on a second memory area and a third memory area of the cell array, each being located adjacent to the first memory area; and

an alert generator configured to, in response to the detect signal, output an alert signal from the volatile memory device to an outside of the volatile memory device.

13. The volatile memory device of claim 12 , wherein the refresh control logic is configured to perform the refresh operation on the second and third memory areas either in response to a refresh command provided from the outside of the volatile memory device, or without a refresh command from the outside of the volatile memory device.

14. The volatile memory device of claim 13 , wherein the disturbance detector is configured to count the number of accesses on the first memory area for a specific period of time.

15. The volatile memory device of claim 13 , wherein the alert signal is shifted from a first logic level to a second logic level in response to the detect signal, and is shifted from the second logic level to the first logic level when the refresh operation on the second memory area and the third memory area is completed.

16. A method of operating a memory device including a memory cell array, the method comprising:

counting a number of times that a first set of memory cells of the memory cell array is accessed during a first time period;

when the counted number of times equals to a reference number is detected, activating an alert signal for a period of time and outputting the alert signal from the memory device to the outside of the memory device; and

performing a refresh operation on a second set of memory cells of the memory cell array,

wherein the second set of memory cells is located adjacent to the first set of memory cells.

17. The method of claim 16 , wherein when the alert signal is output, performing the refresh operation on the second set of memory cells occurs by receiving a refresh command from an outside of the memory device.

18. The method of claim 17 , further comprising:

storing an address related to the second set of memory cells in a register,

wherein performing the refresh operation on the second set of memory cells includes outputting the address by receiving a mode register read command from an outside of the memory device.

19. The method of claim 16 , wherein when the alert signal is output, performing the refresh operation on the second set of memory cells occurs by receiving a refresh command generated internally in the memory device.

20. The method of claim 16 , wherein the period of time of the activated alert signal includes either a first period of time regardless of performing the refresh operation on the second set of memory cells or a second period of time that depends on performing the refresh operation on the second set of memory cells.