IP Library Granted Patent US 10,191,111
Granted Patent B2
US 10,191,111 · App. 14/222,556 · Granted Jan 29, 2019

Synchronized pulsed LADA for the simultaneous acquisition of timing diagrams and laser-induced upsets

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Quick Facts
Patent No.
US 10,191,111
App. No.
14/222,556
Granted
Jan 29, 2019
Kind
B2
Abstract

Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Claims (56)

1. A method, comprising:

sequentially directing a laser beam comprising a train of laser pulses on a plurality of pixel locations within an area of interest of a device under test (DUT);

at each pixel location of the plurality of pixel locations, repetitively applying, at a clock rate established by a clock signal, a test signal that places the DUT in a marginal state and temporally scanning arrival times of the laser pulses at at least one of the pixel locations with respect to the clock signal; and

for each at least one pixel location and at least two of the arrival times, recording a pass/fail result of the DUT so as to determine a probability of failure rate versus arrival time during the test signal for the plurality of pixel locations and arrival times.

2. The method of claim 1 , wherein the laser pulses are configured to have wavelength sufficient to cause two-photon absorption within the DUT.

3. The method of claim 1 , wherein the laser pulses are configured to have wavelength sufficient to cause single-photon absorption within the DUT.

4. The method of claim 1 , wherein recording a pass/fail result of the DUT further comprises recording a first color when the DUT passes and recording a second color when the DUT fails.

5. The method of claim 4 , further comprising generating an image on a monitor using the first and second colors.

6. The method of claim 4 , further comprising generating a plot of failure rate versus arrival time for a selected one of the pixel locations.

7. The method of claim 6 , wherein the first color is one of black and white and the second color is the other of black and white.

8. The method of claim 1 , wherein a flip-flop is situated at at least one pixel location, and the laser pulses are configured to generate a single-upset event in the flip-flop.

9. The method of claim 1 , further comprising correlating a selected plurality of the pixel locations for which pass/fail results indicate a failure rate deviating from 50% with a layout of transistors in a netlist.

10. A method, comprising:

applying to a device under test (DUT) a test pattern comprising a plurality of test signals causing transistors in the DUT to fail with a 50% probability without application of laser pulses;

applying the test pattern repetitively to the DUT while applying laser pulses at selected locations of the DUT, the laser pulses having photon energies sufficient to inject at least one charge carrier pair during the application of the test pattern;

recording test results for each test pattern repetition at each location;

determining locations where the recorded test results diverge from a 50% failure probability in response to the applied laser pulses; and

determining failure rate versus laser pulse arrival time with respect to the test signals at locations wherein the failure rate diverges from 50% failure.

11. The method of claim 1 , further comprising:

generating a plot of failure rate versus arrival time during the test signal for the each of the plurality of pixel locations for which pass/fail results indicate a failure rate deviating from 50%.

12. A system, comprising:

a synch signal generator that produces a synch signal in response to a clock signal associated with a test vector signal applied to a device under test (DUT);

a pulsed laser source generating a pulse train comprising a plurality of laser pulses during a period of the test vector signal applied to the DUT, wherein the pulse train is generated in response to the synch signal from the sync signal generator;

an optical arrangement situated to receive the plurality of laser pulses and to direct each of the laser pulses of the pulse train onto a selected location on the DUT, wherein arrival times of each laser pulse with respect to the test vector signal are different at each of the selected locations; and

a controller configured to detect electrical responses of the DUT at each of the selected locations and identify each of the electrical responses as passing or failing.

13. The system of claim 12 , wherein a pulse rate of the laser pulses is a multiple of a clock rate of the clock signal.

14. The system of claim 12 , wherein the controller is configured to apply a Fourier Transform to the electrical responses.

15. The system of claim 12 , wherein the controller is further configured to produce an image of the DUT indicating each of the selected locations on the DUT as corresponding to a passing electrical response or a failing electrical response.

16. The system of claim 15 , further comprising a display that receives and displays the image.

17. The system of claim 16 , wherein the image includes a first color associated with electrical responses identified as passing and a second color associated with electrical responses identified as failing.

18. The system of claim 17 , wherein the first color is one of black and white and the second color is the other of black and white.

19. The system of claim 12 , wherein the pulsed laser source generates a plurality of pulse trains comprising respective pluralities of laser pulses during respective periods of the test vector signal applied to the DUT, wherein the pulse trains are directed to the DUT so that each selected area receives a laser pulse during each test vector period having a different arrival time with respect to the test vector period, and wherein the controller is configured to detect the electrical response of the DUT at each of the selected locations for each of the received laser pulses, and identify each of the electrical responses as passing or failing.

20. The system of claim 19 , further comprising a memory coupled to the controller so as to store the arrival times with respect to the test vector period of each laser pulse at each of the selected locations and the associated identifications as passing or failing.

21. The system of claim 20 , further comprising a sensor situated to detect reflected portions of the laser pulses of the pulse train from the DUT and to generate intensity signals corresponding to intensities of the detected reflections at each of the selected locations.

22. The system of claim 21 , wherein the memory is further configured to store intensity signals for each of the selected locations on the DUT.

23. The system of claim 19 , wherein the plurality of pulse trains comprises respective pluralities of laser pulses during respective periods of the test vector signal applied to the DUT so that each selected area receives multiple laser pulses at each of the different arrival times with respect to the test vector period, wherein the controller is configured to detect the electrical response of the DUT at each of the selected locations for each of the received laser pulses, and identify each of the electrical responses as passing or failing.

24. The system of claim 23 , further comprising a memory coupled to the controller so as to store the identifications of each of the electrical responses as passing or failing for each of the selected locations on the DUT for each of the plurality of arrival times.

25. The system of claim 23 , further comprising a memory coupled to the controller so as to store a passing rate or a failing rate for each of the selected locations and each of the selected arrival times based on the identifications of the associated electrical responses as passing or failing.

26. The system of claim 25 , wherein the controller is further configured to produce an image of the DUT indicating each of the selected locations on the DUT as corresponding to a passing electrical response or a failing electrical response based on the associated passing rate or failing rate.

27. The system of claim 26 , further comprising a display that receives and displays the image.

28. The system of claim 27 , wherein selected locations associated with a passing rate at above 50% are displayed in a first color and selected locations associated with a passing rate at less than 50% are displayed in a second color.

29. The system of claim 27 , wherein first color is one of black and white and the second color is the other of black and white.

30. The system of claim 23 , further comprising a memory coupled to the controller so as to store an identification of a passing rate or a failing rate for each of the selected locations and each of the selected arrival times based on the identification of the associated electrical responses as passing or failing.

31. The system of claim 30 , further comprising an automated test equipment (ATE) that produces the test vector signal applied to the DUT and the clock signal coupled to the synch signal generator.

32. The system of claim 31 , wherein the test vector signal produced by the ATE has a duration corresponding to at least one clock cycle.

33. The system of claim 12 , wherein the controller is further configured to produce images of the DUT indicating each of the selected locations on the DUT as corresponding to a passing electrical response or a failing electrical response based on the associated passing rates or failing rates for at least two of the arrival times.

34. A system, comprising:

a synch signal generator that produces a synch signal in response to a clock signal associated with a test vector signal applied to a device under test (DUT);

a pulsed laser source generating a plurality of pulse trains comprising respective pluralities of laser pulses during respective periods of the test vector signal applied to the DUT, wherein the pulse trains are generated in response to the synch signal from the sync signal generator;

an optical arrangement situated to receive each of the plurality of pulse trains and to direct the laser pulses of each pulse train onto a corresponding location on the DUT, wherein arrival times of each laser pulse with respect to the test vector signal are different for each of the pulses; and

a controller configured to detect electrical responses of the DUT at each of the selected locations and identify each of the electrical responses as passing or failing.

35. The system of claim 34 , wherein the controller is further configured to produce an image of the DUT indicating each of the selected locations on the DUT as corresponding to a passing electrical response or a failing electrical response.

36. The system of claim 35 , further comprising a display that receives and displays the image.

37. The system of claim 35 , further comprising a memory coupled to the controller so as to store the arrival times with respect to the test vector period of each laser pulse at each of the selected locations and the associated identifications as passing or failing.

38. The system of claim 37 , wherein the pulse laser source produces a plurality of pulse trains that are applied to the DUT at each of the selected locations, plural laser pulses associated with each of the different arrival times so that each selected area receives multiple laser pulses at each of the different arrival times with respect to the test vector period, wherein the controller is configured to detect electrical responses of the DUT at each of the selected locations and identify each of the electrical responses as passing or failing for each of the laser pulses and each of the arrival times.

39. The system of claim 38 , further comprising a memory coupled to the controller so as to store a passing rate or a failing rate for each of the selected locations and each of the selected arrival times based on the identifications of the associated electrical responses as passing or failing.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
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CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2014
From: SERRELS, KEITH; VEDAGARBHA, PRAVEEN; LUNDQUIST, THEODORE
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From: ERINGTON, KENT; BODOH, DANIEL J.
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