Biased reactive refractory metal nitride capped contact of group III-V semiconductor device
View Patent ↗According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.
1. A group III-V semiconductor device including a gate contact, said gate contact comprising:
an electrode stack including a first titanium (Ti), an aluminum (Al) layer over said first titanium (Ti) layer, and a second titanium (Ti) layer over said aluminum (Al) layer;
a biased reactive capping layer formed over said second titanium (Ti) layer, said capping layer comprising biased reactive titanium nitride (TiN);
wherein said gate contact is a gate electrode making Schottky contact with said group III-V semiconductor device.
2. The group III-V semiconductor device of claim 1 , wherein said aluminum (Al) layer of said electrode stack further comprises silicon (Si).
3. The group III-V semiconductor device of claim 1 , wherein said group III-V semiconductor device comprises a high electron mobility transistor (HEMT).
4. A group III-V semiconductor device including a gate contact, said gate contact comprising:
an electrode stack including a first titanium (Ti), an aluminum (Al) layer over said first titanium (Ti) layer, and a second titanium (Ti) layer over said aluminum (Al) layer;
a biased reactive capping layer formed over said second titanium (Ti) layer, said capping layer comprising biased reactive titanium nitride (TiN);
wherein said gate contact is situated over a gate insulator layer to form a gate of said group III-V semiconductor device.
5. The group III-V semiconductor device of claim 4 , wherein said aluminum (Al) layer of said electrode stack further comprises silicon (Si).
6. The group III-V semiconductor device of claim 4 , wherein said group III-V semiconductor device comprises a high electron mobility transistor (HEMT).