IP Library Granted Patent US 9,499,397
Granted Patent B2
US 9,499,397 · App. 14/230,273 · Granted Nov 22, 2016

Microelectronic packages having axially-partitioned hermetic cavities and methods for the fabrication thereof

Inventors: Philip H. Bowles (Gilbert, AZ); Stephen R. Hooper (Mesa, AZ)
Assignee: Freescale Semiconductor, Inc.
B81B7/02B81B2201/0235B81B2201/0242
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Quick Facts
Patent No.
US 9,499,397
App. No.
14/230,273
Granted
Nov 22, 2016
Kind
B2
Abstract

Microelectronic packages and methods for producing microelectronic packages are provided. In one embodiment, the method includes bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece. The first MEMS die and cap piece are bonded such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer. A second MEMS die having a second MEMS transducer structure thereon is further bonded to one of the cap piece and the second MEMS die. The second MEMS die and the cap piece are bonded such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer. The second hermetically-sealed cavity contains a different internal pressure than does the first hermetically-sealed cavity.

Claims (32)

1. A method for fabricating a microelectronic package, comprising:

bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer;

bonding a second MEMS die having a second MEMS transducer structure thereon to one of the cap piece and the second MEMS die such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer, the second hermetically-sealed cavity containing a different internal pressure than does the first hermetically-sealed cavity;

removing a portion of the second MEMS die and the cap piece overlying a bond pad shelf on the first MEMS die to reveal the bond pad shelf and a plurality of bonds pads thereon; and

forming wire bonds in contact with the plurality of bonds to electrically interconnect the first MEMS die with the second MEMS die.

2. The method of claim 1 wherein the first MEMS die, the second MEMS die, and the cap piece are bonded in wafer form to produce a wafer stack; and

wherein the method further comprises singulating the wafer stack to produce the microelectronic packages along with a plurality of other microelectronic packages.

3. The method of claim 1 wherein the first MEMS transducer structure comprises a gyroscope transducer structure, wherein the second MEMS transducer structure comprises an accelerometer transducer structure, and wherein the first hermetically-sealed cavity contains an internal pressure less than the second MEMS transducer structure.

4. The method of claim 1 wherein the first cap piece is bonded to the second MEMS die such that an Application Specific Integrated Circuit formed on the cap piece is exposed to the pressure within the second hermetically-sealed cavity.

5. The method of claim 4 wherein the second MEMS transducer structure comprises a gyroscope transducer structure, and wherein the pressure within the second hermetically-sealed cavity is less than the pressure within the first hermetically-sealed cavity.

6. The method of claim 1 wherein the first MEMS die is bonded to the cap piece utilizing a first bonding material, and wherein the second MEMS die is bonded to one of the cap piece and the second MEMS die utilizing a second bonding material different than the first bonding material.

7. The method of claim 6 wherein the first bonding material has a greater bonding temperature than does the second bonding material.

8. The method of claim 1 wherein the second MEMS die is bonded to the cap piece opposite the first MEMS die such that the first and second MEMS die are stacked in a face-to-face relationship.

9. The method of claim 1 wherein the second MEMS die is bonded to the first MEMS die such that the first and second MEMS die are stacked in a face-to-back relationship.

10. The method of claim 9 further comprising etching a recess into the backside of the second MEMS die prior to bonding to the first MEMS die, the recess enlarging the volume of the first hermetically-sealed cavity.

11. The method of claim 1 further comprising forming electrical connections to through silicon vias formed through at least one of the first and second MEMS die to interconnect the first and second MEMS die with an input/out interface accessible from the exterior of the microelectronic package.

12. A method for fabricating microelectronic packages, comprising:

bonding a first wafer to a second wafer to produce a two wafer stack comprising a first array of Microelectromechanical Systems (MEMS) transducer structures enclosed by a first plurality of hermetic cavities each containing a first predetermined pressure;

bonding a third wafer to the two wafer stack to produce a three wafer stack comprising a second array of MEMS transducer structures enclosed by a second plurality of hermetic cavities each containing a second predetermined pressure different than the first predetermined pressure; and

singulating the three wafer stack into a plurality of die-cap stacks each including axially-partitioned hermetic cavities enclosing different MEMS transducer structures and containing different internal pressures.

13. The method of claim 12 wherein the first array of MEMS transducer structures are formed on the first wafer, wherein the second array of MEMS transducer structures are formed on the third wafer, and wherein third wafer is bonded to the second wafer opposite the first wafer to produce the three wafer stack.

14. The method of claim 12 wherein the first array of MEMS transducer structures are formed on the first wafer, wherein the second array of MEMS transducer structures are formed on the third wafer, and wherein third wafer is bonded to the first wafer opposite the second wafer to produce the three wafer stack.

15. The method of claim 12 wherein the first wafer is bonded to the second wafer utilizing a first electrically-conductive bonding material, and wherein the second wafer is bonded to the two wafer stack utilizing a second electrically-conductive bonding material having a lower bonding temperature than does the first electrically-conductive bonding material.

16. The method of claim 12 wherein the first array of MEMS structures is formed on the first wafer, and wherein the second array of MEMS structures is formed on one of the second and third wafers.

17. The method of claim 12 wherein, for each of the plurality of die-cap stacks defined by singulation of the three wafer stack, the axially-partitioned hermetic cavities overlap vertically as taken along a centerline of the die-cap stack.

18. The method of claim 13 wherein, for each of the plurality of die-cap stacks defined by singulation of the three wafer stack, the axially-partitioned hermetic cavities are partitioned by a singulated piece of one of the second and third wafers.

19. A method for fabricating a microelectronic package, comprising:

bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer;

bonding a second MEMS die having a second MEMS transducer structure thereon to the first MEMS die such that the first and second MEMS die are stacked in a face-to-back relationship and such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer, the second hermetically-sealed cavity containing a different internal pressure than does the first hermetically-sealed cavity; and

etching a recess into the backside of the second MEMS die prior to bonding to the first MEMS die, the recess enlarging the volume of the first hermetically-sealed cavity.

20. The method of claim 19 wherein the first MEMS die, the second MEMS die, and the cap piece are bonded in wafer form to produce a wafer stack; and

wherein the method further comprises singulating the wafer stack to produce the microelectronic packages along with a plurality of other microelectronic packages.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0438. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0136 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0498 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0479 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0438 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0763 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0522 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 032845/0497 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2014
From: BOWLES, PHILIP H.; HOOPER, STEPHEN R.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 032559/0461 →
Continuity (1)
Related Publication 20150274515A1 · Oct 1, 2015