IP Library Granted Patent US 9,214,454
Granted Patent B2
US 9,214,454 · App. 14/230,388 · Granted Dec 15, 2015

Batch process fabrication of package-on-package microelectronic assemblies

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,214,454
App. No.
14/230,388
Granted
Dec 15, 2015
Kind
B2
Abstract

A microelectronic assembly can be made by joining first and second subassemblies by electrically conductive masses to connect electrically conductive elements on support elements of each subassembly. A patterned layer of photo-imageable material may overlie a surface of one of the support elements and have openings with cross-sectional dimensions which are constant or monotonically increasing with height from the surface of that support element, where the masses extend through the openings and have dimensions defined thereby. An encapsulation can be formed by flowing an encapsulant into a space between the joined first and second subassemblies.

Claims (23)

1. A microelectronic assembly, comprising:

first and second support elements each having a first surface facing in an outwardly direction of the assembly and each having a second surface facing in an inwardly direction of the assembly towards the second surface of the other of the first and second support elements respectively, and including at least one of: first terminals at the first surface of the first support element, or second terminals at the first surface of the second support element;

electrically conductive first elements at the second surface of the first support element;

a patterned layer of photo-imageable material overlying the second surface of the first support element and having openings aligned with the electrically conductive first elements, each opening having a cross-sectional dimension which is constant or increasing with a height from the second surface of the first support element;

electrically conductive masses of bonding material electrically coupled with and projecting above the electrically conductive first elements through the corresponding openings of the patterned layer, each mass having a cross-sectional dimension which is defined by a cross-sectional dimension of the corresponding opening through which it projects;

a microelectronic element mounted to the second surface of one of the first or the second support elements;

electrically conductive second elements at the second surface of the second support element, the electrically conductive second elements electrically coupled with the masses and electrically coupled with the first elements through the masses; and

an encapsulation overlying the second surface of the second support element, a surface of the patterned layer and contacting at least some of the masses, the masses extending through at least a portion of the encapsulation.

2. The microelectronic assembly as claimed in claim 1 ,

wherein the assembly comprises the first terminals at the first surface of the first support element, and the second terminals at the first surface of the second support element, the first terminals being electrically coupled with the second terminals through the electrically conductive first elements, the electrically conductive second elements, and the masses therebetween, or

the assembly includes one of:

the first terminals at the first surface of the first support element, the first terminals being electrically coupled with the electrically conductive second elements through the masses therebetween; or

the second terminals at the first surface of the second support element, the second terminals being electrically coupled with the electrically conductive first elements through the masses therebetween.

3. The microelectronic assembly as claimed in claim 1 , wherein the masses comprise bulbous portions where the masses extend through the at least a portion of the encapsulation.

4. The microelectronic assembly as claimed in claim 2 , wherein the encapsulation is formed in contact with the surface of the patterned layer and in contact with the second surface of the second support element.

5. The microelectronic assembly as claimed in claim 2 , wherein the microelectronic element has a face facing away from the second support element, and the encapsulation is a first encapsulation formed in contact with at least one of: the face of the microelectronic element or a second encapsulation formed on the face of the microelectronic element.

6. The microelectronic assembly as claimed in claim 5 , wherein the microelectronic assembly comprises the second encapsulation formed on the face of the microelectronic element, and the first encapsulation is formed in contact with the second encapsulation.

7. A stacked multi-chip microelectronic assembly including the microelectronic assembly as claimed in claim 2 , and a microelectronic package overlying the first surface of the first support element, the microelectronic package having terminals connected with the first terminals of the microelectronic assembly.

8. The stacked multi-chip microelectronic assembly as claimed in claim 7 , wherein a minimum pitch of the first terminals is larger than a minimum pitch of the electrically conductive first elements.

9. The stacked multi-chip microelectronic assembly as claimed in claim 8 , wherein the minimum pitch of the first terminals is the same as a minimum pitch of the second terminals.

10. A stacked multi-chip microelectronic assembly including the microelectronic assembly as claimed in claim 2 , wherein the microelectronic assembly includes the second terminals but not the first terminals, and the second terminals are electrically coupled with the electrically conductive first elements through the masses therebetween.

11. The stacked multi-chip microelectronic assembly as claimed in claim 10 , further comprising a second microelectronic element mounted to the first surface of the first support element, and a second encapsulation contacting the first surface of the first support element and surfaces of the second microelectronic element.

12. The stacked multi-chip microelectronic assembly as claimed in claim 11 , wherein the second microelectronic element is electrically coupled with the second terminals through the electrically conductive first elements and through the masses which are electrically coupled therebetween.

Assignments (6)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0661 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073689/0793 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2014
From: HABA, BELGACEM; MOHAMMED, ILYAS; WANG, LIANG
To: INVENSAS CORPORATION
Reel/Frame 033859/0635 →