Strobe-offset control circuit
A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.
1. An integrated circuit (IC) memory controller comprising:
a first pin to receive a first data signal;
a first adjustable delay element to delay the received first data signal and generate a first delayed data signal;
a second pin to receive a second data signal;
a second adjustable delay element to delay the received second data signal and generate a second delayed data signal;
a pin to receive a strobe signal;
a first sampling circuit to sample the first delayed data signal based on the strobe signal; and
a second sampling circuit to sample the second delayed data signal based on the received strobe signal.
2. The IC memory controller according to claim 1 , further comprising storage to store each of first and second delay values corresponding to the delays imparted to the first and second data signals.
3. The IC memory controller according to claim 1 , embodied as a field programmable gate array (FPGA) device.
4. The IC memory controller according to claim 1 , wherein the first and second data signals are delayed to compensate for timing offset between the received first and second data signals.
5. The IC memory controller according to claim 4 , further comprising:
a first timing signal delay element associated with the first pin; and
a second timing signal delay element associated with the second pin;
wherein each of the first and second timing signal delay elements impart first and second delays to the strobe signal.
6. The IC memory controller according to claim 1 , wherein:
each of the first and second delay elements comprise locked-loop circuits having plural serially connected delay elements.
7. The IC memory controller according to claim 6 , wherein the first delay value is used to select delay elements of the first delay circuit and the second delay value is used to select delay elements of the second delay circuit.
8. The IC memory controller according to claim 1 , further comprising a calibration strobe delay element to impart a calibrated delay to the strobe signal.
9. The IC memory controller according to claim 1 , further comprising a calibration circuit to, in a calibration mode, determine the first and second delay values.
10. A method of operation in an IC memory controller, the method comprising:
receiving first and second data signals from a memory device at respective first and second pins;
aligning the received first and second data signals with a strobe signal, the aligning comprising
imparting a first delay to the first data signal, the first delay corresponding to a first delay value,
imparting a second delay to the second data signal, the second delay corresponding to a second delay value.
11. The method according to claim 10 , further comprising:
in a calibration mode,
determining the first and second delay values; and
storing the first and second delay values.
12. The method according to claim 11 , wherein:
during the receiving mode,
the imparting the first and second delays includes retrieving the stored first and second delay values.
13. The method according to claim 12 , wherein:
the first and second data signals are delayed by the first and second delay values.
14. The method according to claim 11 , further comprising:
during the calibration mode,
calibrating a timing signal delay value corresponding to a delay for application to the strobe signal.
15. The method according to claim 14 , further comprising:
during the calibration mode,
storing the calibrated timing delay value.
16. A Field Programmable Gate Array (FPGA) device comprising:
a memory controller interface, the memory controller interface including data pins, the data pins to receive respective data signals;
calibration circuitry to, in a calibration mode, determine delay values corresponding to delays to impart to, for each pin, a received data signal to align the data signals with a strobe signal for data sampling operations, each pin associated with a given delay value;
alignment circuits corresponding to each data pin, each alignment circuit including delay circuitry responsive to a given determined delay value;
storage to store the determined delay values.
17. The FPGA according to claim 16 , wherein the calibration circuitry determines a timing signal delay to impart to the strobe signal.
18. The FPGA according to claim 17 , wherein each alignment circuit includes a timing signal delay element responsive to the determined timing signal delay.
19. The FPGA according to claim 16 , wherein the alignment circuits include respective locked-loop circuits responsive to different ones of the determined delay values.
20. The FPGA according to claim 16 , wherein the calibration circuitry includes a calibration strobe delay element to impart a calibrated delay to the strobe signal.