IP Library › Granted Patent US 9,111,852
Granted Patent B2
US 9,111,852 · App. 14/235,784 · Granted Aug 18, 2015

Semiconductor device

Inventors: Masatoshi Aketa (Kyoto, JP); Yuta Yokotsuji (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01L29/2003H01L29/08H01L29/1602H01L29/1608H01L29/861H01L29/8613H01L29/872
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Quick Facts
Patent No.
US 9,111,852
App. No.
14/235,784
Granted
Aug 18, 2015
Kind
B2
Abstract

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V th of 0.3 V to 0.7 V and a leakage current J r of 1×10 −9 A/cm 2 to 1×10 −4 A/cm 2 in a rated voltage V R .

Claims (31)

1. A semiconductor device comprising:

a first conductivity type semiconductor layer made of a wide bandgap semiconductor, and

a Schottky electrode formed to come into contact with a surface of the semiconductor layer,

wherein a threshold voltage V th is 0.3 V to 0.7 V, and a leakage current J r in a rated voltage V R is 1×10 9 A/cm 2 to 1×10 −4 A/cm 2 .

2. The semiconductor device according to claim 1 , wherein a breakdown voltage V B of the semiconductor device is 700 V or more, and

the rated voltage V R of the semiconductor device is 50 to 90% of the breakdown voltage V B that is 700 V or more.

3. The semiconductor device according to claim 1 , wherein on-resistance R on ·A of the semiconductor device is 0.3 mΩ·cm 2 to 3 mΩ·cm 2 .

4. The semiconductor device according to claim 1 , wherein a trench having a side wall and a bottom wall is formed on a side of the surface of the semiconductor layer, and

an edge part of the bottom wall of the trench has a curvature radius R that satisfies the following formula (1):

0.01 L<R< 10 L   (1)

(in formula (1), L designates a linear distance between edge parts facing each other along a width direction of the trench.)

5. The semiconductor device according to claim 4 , wherein the semiconductor layer includes a second conductivity type electric-field-moderating portion that is selectively formed at the bottom wall of the trench and at the edge part of the bottom wall.

6. The semiconductor device according to claim 5 , wherein the Schottky electrode is formed so as to be embedded in the trench, and

the electric-field-moderating portion has a contact portion at the bottom wall of the trench and the contact portion makes an ohmic contact with the Schottky electrode embedded in the trench.

7. The semiconductor device according to claim 4 , wherein the electric-field-moderating portion is formed to straddle between the edge part of the bottom wall of the trench and the side wall of the trench.

8. The semiconductor device according to claim 7 , wherein the electric-field-moderating portion is formed to lead to an opening end of the trench along the side wall of the trench.

9. The semiconductor device according to claim 4 , wherein the trench includes a taper trench that has the bottom wall having a planar shape and the side wall inclined at an angle exceeding 90° with respect to the bottom wall having a planar shape.

10. The semiconductor device according to claim 4 , wherein the semiconductor layer has a first part of a first conductivity type to which a first electric field is applied when a reverse voltage is applied and a second part of the first conductivity type to which a second electric field relatively higher than the first electric field is applied, and

the Schottky electrode includes a first electrode that forms a first Schottky barrier with the first part and a second electrode that forms a second Schottky barrier with the second part, the second Schottky barrier being relatively higher than the first Schottky barrier.

11. The semiconductor device according to claim 10 , wherein the first part of the semiconductor layer is formed at a peripheral edge of the opening end of the trench in a surface layer part of the semiconductor layer, whereas the second part of the semiconductor layer is formed at a part adjoining the peripheral edge in the surface layer part of the semiconductor layer.

12. The semiconductor device according to claim 4 , wherein the semiconductor layer includes a base drift layer that has a first impurity concentration and a low-resistance drift layer that is formed on the base drift layer and that has a second impurity concentration relatively higher than the first impurity concentration, and

the trench is formed so that a deepest part thereof reaches the low-resistance drift layer, and a part of the semiconductor layer is partitioned as a unit cell.

13. The semiconductor device according to claim 12 , wherein the first impurity concentration of the base drift layer becomes lower in proportion to an approach to the surface from a reverse surface of the semiconductor layer.

14. The semiconductor device according to claim 12 , wherein the second impurity concentration of the low-resistance drift layer is constant in proportion to an approach to the surface from the reverse surface of the semiconductor layer.

15. The semiconductor device according to claim 12 , wherein the second impurity concentration of the low-resistance drift layer becomes lower in proportion to an approach to the surface from the reverse surface of the semiconductor layer.

16. The semiconductor device according to claim 12 , wherein the semiconductor layer further includes an obverse-surface drift layer that is formed on the low-resistance drift layer and that has a third impurity concentration relatively lower than the second impurity concentration.

17. The semiconductor device according to claim 12 , wherein the semiconductor layer further includes a substrate and a buffer layer that is formed on the substrate and that has a fourth impurity concentration relatively higher than the first impurity concentration.

18. The semiconductor device according to claim 4 , wherein the trench includes a stripe trench formed in a stripe manner.

19. The semiconductor device according to claim 1 , wherein the trench includes a lattice trench formed in a grid-like manner.

20. The semiconductor device according to claim 1 , wherein an insulation breakdown electric field of the wide bandgap semiconductor is greater than 1 MV/cm.

21. The semiconductor device according to claim 1 , wherein the wide bandgap semiconductor is made of SiC, or GaN, or diamond.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2014
From: AKETA, MASATOSHI; YOKOTSUJI, YUTA
To: ROHM CO., LTD.
Reel/Frame 032200/0618 →
Priority Claims (1)
JP 2011-165660 · Jul 28, 2011 · national
Continuity (1)
Related Publication 20140203299A1 · Jul 24, 2014