IP Library Granted Patent US 9,123,542
Granted Patent B2
US 9,123,542 · App. 14/237,147 · Granted Sep 1, 2015

Plasma etching method

Inventors: Shoichi Murakami (Hyogo, JP); Naoya Ikemoto (Hyogo, JP)
Assignee: SPP Technologies Co., Ltd.
H01L21/0475H01L21/3065H01L21/3081H01L21/3085H01L21/76813H01L21/76822H01L29/1608
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Quick Facts
Patent No.
US 9,123,542
App. No.
14/237,147
Granted
Sep 1, 2015
Kind
B2
Abstract

A plasma etching method forms a tapered recess portion in a wide-gap semiconductor substrate. The method includes forming on the substrate K an etching film having an etching speed higher than that of the substrate K, and forming a mask M having an opening on the high-speed etching film. The substrate K with the etching film and the mask is then placed on a platen and heated to a temperature equal to or higher than 200 ° C., a plasma is generated from an etching gas supplied into a processing chamber, and a bias potential is applied to the platen to etch substrate.

Claims (17)

1. A plasma etching method of plasma etching a wide-gap semiconductor substrate having at least a wide-gap semiconductor layer and placed on a platen arranged in a processing chamber using a plasma generated from a reactive etching gas, comprising:

a deposition step of forming a high speed etching film directly on a surface of the wide-gap semiconductor layer, the high speed etching film comprising a component which is etched at a higher speed than a component of the wide-gap semiconductor layer by reactive species generated by generating the plasma from the reactive etching gas,

a mask forming step of forming a mask having an opening on the high speed etching film formed on the surface of the wide-gap semiconductor substrate; and

an etching step of placing the wide-gap semiconductor substrate on the platen arranged in the processing chamber, heating the wide-gap semiconductor substrate to a temperature equal to or higher than 200 ° C., and supplying the reactive etching gas into the processing chamber to generate the plasma and applying a bias potential to the platen on which the wide-gap semiconductor substrate is placed, thereby etching, through the opening, the high speed etching film and the wide-gap semiconductor layer by the plasma generated from the reactive etching gas,

the etching step of etching the high speed etching film through the opening to expose the wide-gap semiconductor layer and then etching the wide-gap semiconductor layer while further etching the high speed etching film to expose a portion located under the mask of the wide-gap semiconductor layer, thereby forming a tapered etching structure in the wide-gap semiconductor layer.

2. The plasma etching method according to claim 1 , in which the high speed etching film comprises at least one of titanium, titanium nitride, amorphous silicon, polysilicon, tungsten silicide and silicon nitride.

3. The plasma etching method according to claim 1 , in which the wide-gap semiconductor substrate is a substrate comprising silicon carbide.

4. The plasma etching method according to claim 1 , in which the reactive etching gas is a fluorine-containing gas.

5. The plasma etching method according to claim 1 , in which the deposition step is performed by a vapor deposition, and, in the deposition step, a deposition condition is set so that the high speed etching film is deposited with a film quality which allows a side wall surface of an etching structure formed in the etching step to have a desired angle to a bottom surface thereof, and the high speed etching film is deposited under the set deposition condition,

the deposition condition being set based on a correlation between the deposition condition, the film quality of the high speed etching film, and the angle of the side wall surface to the bottom surface of the etching structure formed in the etching step, where the film quality changes in accordance with the deposition condition and the angle is smaller when the high speed etching film is easier to etch.

6. The plasma etching method according to claim 5 , in which the deposition condition includes at least one of a supply flow rate of a source gas for deposition supplied into a process chamber, a supply flow rate of a carrier gas supplied into the process chamber, a pressure inside the process chamber, and a power applied to electrode.

7. The plasma etching method according to claim 1 , in which:

the high speed etching film comprises at least one of amorphous silicon, polysilicon, tungsten silicide and silicon nitride, and

the deposition step is performed by a vapor deposition, and the high speed etching film is deposited under a deposition condition which is set so that the high speed etching film has a predetermined refractive index.

8. The plasma etching method according to claim 7 , in which the deposition condition includes at least one of a supply flow rate of a source gas for deposition supplied into a process chamber, a supply flow rate of a carrier gas supplied into the process chamber, a pressure inside the process chamber, and a power applied to electrode.

9. The plasma etching method according to claim 1 , in which the deposition step is performed by a vapor deposition, and, in the deposition step, a film thickness condition is set so that the high speed etching film is deposited with a film thickness which allows side wall surface an etching structure formed in the etching step to have a desired angle to a bottom surface thereof, and the high speed etching film is deposited under the set film thickness condition,

the film thickness condition being set based on a correlation between the film thickness condition, the film thickness of the high speed etching film, and the angle of the side wall surface to the bottom surface of the etching structured formed in the etching step, where the film thickness changes in accordance with the film thickness condition and the angle is smaller when the film thickness is thicker.

Assignments (2)
CHANGE OF ADDRESS Recorded Sep 10, 2020
From: SPP TECHNOLOGIES CO., LTD.
To: SPP TECHNOLOGIES CO., LTD.
Reel/Frame 053745/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2014
From: MURAKAMI, SHOICHI; IKEMOTO, NAOYA
To: SPP TECHNOLOGIES CO., LTD
Reel/Frame 032139/0729 →
Priority Claims (1)
JP 2011-193129 · Sep 5, 2011 · national
Continuity (1)
Related Publication 20140187048A1 · Jul 3, 2014