DRAM refresh method and system

1. A method of operating a DRAM, the method comprising:

refreshing the DRAM in a memory system organized into rows of memory cells, each of said cells having an associated data retention time, said memory system arranged to refresh predefined blocks of said memory cells simultaneously;

for each predefined block of memory cells that are to be refreshed simultaneously, determining a minimum data retention time for the memory cells in each of the predefined blocks; and

creating an asymmetric refresh sequence which specifies the order in which said blocks of memory cells are to be refreshed, such that said blocks of memory cells having the shortest minimum data retention times are refreshed more often than the blocks of memory cells having longer minimum data retention times.

2. The method of claim 1 , wherein each of said blocks of memory cells comprises one or more rows of memory cells.

3. The method of claim 1 , further comprising refreshing said blocks of memory cells in accordance with said asymmetric refresh sequence.

4. The method of claim 1 , wherein each of said blocks of memory cells is refreshed in response to a respective refresh command.

5. The method of claim 1 , wherein each of said blocks of memory cells is refreshed in response to a respective refresh command, further comprising refreshing said blocks of memory cells in accordance with said asymmetric refresh sequence, wherein said memory system must comply with a requirement that x refresh commands be executed every y ms, said method arranged such that x refresh commands are executed every y ms.

6. The method of claim 5 , wherein said asymmetric refresh sequence is arranged such that the number of times that each block of memory cells is refreshed in y ms is equal to a power of 2.

7. The method of claim 5 , wherein each of said blocks of memory cells is a bank of memory cells comprising R rows, said memory system arranged such that each refresh command refreshes N rows, where N=R/8192.

8. The method of claim 5 , wherein said memory system must comply with a requirement that 8192 refresh commands be executed every 64 ms.

9. The method of claim 1 , wherein said DRAM reside on a memory module which includes a memory buffer that operates as an interface between a host controller and said DRAM, said minimum data retention times determined for said blocks of memory cells using test circuitry contained within said memory buffer.

10. The method of claim 9 , wherein said test circuitry comprises MemBIST circuitry.

11. The method of claim 9 , wherein said asymmetric refresh sequence is stored in DRAM that resides on said memory module.

12. The method of claim 9 , wherein said asymmetric refresh sequence is stored in DRAM by said memory buffer at boot time.

13. The method of claim 1 , wherein said asymmetric refresh sequence is stored in an EPROM device.

14. The method of claim 1 , wherein said asymmetric refresh sequence is stored as a linked list structure.

15. The method of claim 1 , wherein said asymmetric refresh sequence is stored as a FAT tree structure.

16. The method of claim 1 , wherein said asymmetric refresh sequence is stored as a binary tree structure.

17. The method of claim 1 , wherein said asymmetric refresh sequence is stored in non-data-containing DRAM, in rows that get refreshed.

18. The method of claim 1 , wherein each of said blocks of memory cells is refreshed in response to a respective refresh command, each of said predefined memory blocks that is to be refreshed has an associated ID, and said asymmetric refresh sequence comprises a plurality of loops with a predetermined number of refresh commands per loop, each loop having an associated ID, further comprising creating a table which specifies:

the ID of the next predefined memory block to be refreshed; and

the ID of the next loop.